1XILINX AXI ETHERNET Device Tree Bindings 2-------------------------------------------------------- 3 4Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core 5provides connectivity to an external ethernet PHY supporting different 6interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two 7segments of memory for buffering TX and RX, as well as the capability of 8offloading TX/RX checksum calculation off the processor. 9 10Management configuration is done through the AXI interface, while payload is 11sent and received through means of an AXI DMA controller. This driver 12includes the DMA driver code, so this driver is incompatible with AXI DMA 13driver. 14 15For more details about mdio please refer phy.txt file in the same directory. 16 17Required properties: 18- compatible : Must be one of "xlnx,axi-ethernet-1.00.a", 19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a" 20- reg : Address and length of the IO space, as well as the address 21 and length of the AXI DMA controller IO space, unless 22 axistream-connected is specified, in which case the reg 23 attribute of the node referenced by it is used. 24- interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA, 25 and optionally Ethernet core. If axistream-connected is 26 specified, the TX/RX DMA interrupts should be on that node 27 instead, and only the Ethernet core interrupt is optionally 28 specified here. 29- phy-handle : Should point to the external phy device. 30 See ethernet.txt file in the same directory. 31- xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware 32 33Optional properties: 34- phy-mode : See ethernet.txt 35- xlnx,phy-type : Deprecated, do not use, but still accepted in preference 36 to phy-mode. 37- xlnx,txcsum : 0 or empty for disabling TX checksum offload, 38 1 to enable partial TX checksum offload, 39 2 to enable full TX checksum offload 40- xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload 41- clocks : AXI bus clock for the device. Refer to common clock bindings. 42 Used to calculate MDIO clock divisor. If not specified, it is 43 auto-detected from the CPU clock (but only on platforms where 44 this is possible). New device trees should specify this - the 45 auto detection is only for backward compatibility. 46- axistream-connected: Reference to another node which contains the resources 47 for the AXI DMA controller used by this device. 48 If this is specified, the DMA-related resources from that 49 device (DMA registers and DMA TX/RX interrupts) rather 50 than this one will be used. 51 - mdio : Child node for MDIO bus. Must be defined if PHY access is 52 required through the core's MDIO interface (i.e. always, 53 unless the PHY is accessed through a different bus). 54 55Example: 56 axi_ethernet_eth: ethernet@40c00000 { 57 compatible = "xlnx,axi-ethernet-1.00.a"; 58 device_type = "network"; 59 interrupt-parent = <µblaze_0_axi_intc>; 60 interrupts = <2 0 1>; 61 clocks = <&axi_clk>; 62 phy-mode = "mii"; 63 reg = <0x40c00000 0x40000 0x50c00000 0x40000>; 64 xlnx,rxcsum = <0x2>; 65 xlnx,rxmem = <0x800>; 66 xlnx,txcsum = <0x2>; 67 phy-handle = <&phy0>; 68 axi_ethernetlite_0_mdio: mdio { 69 #address-cells = <1>; 70 #size-cells = <0>; 71 phy0: phy@0 { 72 device_type = "ethernet-phy"; 73 reg = <1>; 74 }; 75 }; 76 }; 77