1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/net/wireless/mediatek,mt76.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: MediaTek mt76 wireless devices 9 10maintainers: 11 - Felix Fietkau <nbd@nbd.name> 12 - Lorenzo Bianconi <lorenzo@kernel.org> 13 - Ryder Lee <ryder.lee@mediatek.com> 14 15description: | 16 This node provides properties for configuring the MediaTek mt76xx 17 wireless device. The node is expected to be specified as a child 18 node of the PCI controller to which the wireless chip is connected. 19 Alternatively, it can specify the wireless part of the MT7628/MT7688 20 or MT7622/MT7986 SoC. 21 22allOf: 23 - $ref: ieee80211.yaml# 24 25properties: 26 compatible: 27 enum: 28 - mediatek,mt76 29 - mediatek,mt7628-wmac 30 - mediatek,mt7622-wmac 31 - mediatek,mt7986-wmac 32 33 reg: 34 minItems: 1 35 maxItems: 3 36 description: 37 MT7986 should contain 3 regions consys, dcm, and sku, in this order. 38 39 interrupts: 40 maxItems: 1 41 42 power-domains: 43 maxItems: 1 44 45 memory-region: 46 maxItems: 1 47 48 resets: 49 maxItems: 1 50 description: 51 Specify the consys reset for mt7986. 52 53 reset-names: 54 const: consys 55 56 clocks: 57 maxItems: 2 58 description: 59 Specify the consys clocks for mt7986. 60 61 clock-names: 62 items: 63 - const: mcu 64 - const: ap2conn 65 66 mediatek,infracfg: 67 $ref: /schemas/types.yaml#/definitions/phandle 68 description: 69 Phandle to the infrastructure bus fabric syscon node. 70 This property is MT7622 specific 71 72 ieee80211-freq-limit: true 73 74 mediatek,eeprom-data: 75 $ref: /schemas/types.yaml#/definitions/uint32-array 76 description: 77 EEPROM data embedded as array. 78 79 mediatek,mtd-eeprom: 80 $ref: /schemas/types.yaml#/definitions/phandle-array 81 items: 82 - items: 83 - description: phandle to MTD partition 84 - description: offset containing EEPROM data 85 description: 86 Phandle to a MTD partition + offset containing EEPROM data 87 88 big-endian: 89 $ref: /schemas/types.yaml#/definitions/flag 90 description: 91 Specify if the radio eeprom partition is written in big-endian 92 93 mediatek,eeprom-merge-otp: 94 type: boolean 95 description: 96 Merge EEPROM data with OTP data. Can be used on boards where the flash 97 calibration data is generic and specific calibration data should be 98 pulled from the OTP ROM 99 100 mediatek,disable-radar-background: 101 type: boolean 102 description: 103 Disable/enable radar/CAC detection running on a dedicated offchannel 104 chain available on some hw. 105 Background radar/CAC detection allows to avoid the CAC downtime 106 switching on a different channel during CAC detection on the selected 107 radar channel. 108 109 led: 110 type: object 111 $ref: /schemas/leds/common.yaml# 112 additionalProperties: false 113 properties: 114 led-active-low: 115 description: 116 LED is enabled with ground signal. 117 type: boolean 118 119 led-sources: 120 maxItems: 1 121 122 power-limits: 123 type: object 124 additionalProperties: false 125 patternProperties: 126 "^r[0-9]+": 127 type: object 128 additionalProperties: false 129 properties: 130 regdomain: 131 $ref: /schemas/types.yaml#/definitions/string 132 description: 133 Regdomain refers to a legal regulatory region. Different 134 countries define different levels of allowable transmitter 135 power, time that a channel can be occupied, and different 136 available channels 137 enum: 138 - FCC 139 - ETSI 140 - JP 141 142 patternProperties: 143 "^txpower-[256]g$": 144 type: object 145 additionalProperties: false 146 patternProperties: 147 "^b[0-9]+$": 148 type: object 149 additionalProperties: false 150 properties: 151 channels: 152 $ref: /schemas/types.yaml#/definitions/uint32-array 153 minItems: 2 154 maxItems: 2 155 description: 156 Pairs of first and last channel number of the selected 157 band 158 159 rates-cck: 160 $ref: /schemas/types.yaml#/definitions/uint8-array 161 minItems: 4 162 maxItems: 4 163 description: 164 4 half-dBm per-rate power limit values 165 166 rates-ofdm: 167 $ref: /schemas/types.yaml#/definitions/uint8-array 168 minItems: 8 169 maxItems: 8 170 description: 171 8 half-dBm per-rate power limit values 172 173 rates-mcs: 174 $ref: /schemas/types.yaml#/definitions/uint8-matrix 175 description: 176 Sets of per-rate power limit values for 802.11n/802.11ac 177 rates for multiple channel bandwidth settings. 178 Each set starts with the number of channel bandwidth 179 settings for which the rate set applies, followed by 180 either 8 or 10 power limit values. The order of the 181 channel bandwidth settings is 20, 40, 80 and 160 MHz. 182 maxItems: 4 183 items: 184 minItems: 9 185 maxItems: 11 186 187 rates-ru: 188 $ref: /schemas/types.yaml#/definitions/uint8-matrix 189 description: 190 Sets of per-rate power limit values for 802.11ax rates 191 for multiple channel bandwidth or resource unit settings. 192 Each set starts with the number of channel bandwidth or 193 resource unit settings for which the rate set applies, 194 followed by 12 power limit values. The order of the 195 channel resource unit settings is RU26, RU52, RU106, 196 RU242/SU20, RU484/SU40, RU996/SU80 and RU2x996/SU160. 197 items: 198 minItems: 13 199 maxItems: 13 200 201 txs-delta: 202 $ref: /schemas/types.yaml#/definitions/uint32-array 203 description: 204 Half-dBm power delta for different numbers of antennas 205 206required: 207 - compatible 208 - reg 209 210unevaluatedProperties: false 211 212examples: 213 - | 214 pcie0 { 215 #address-cells = <3>; 216 #size-cells = <2>; 217 wifi@0,0 { 218 compatible = "mediatek,mt76"; 219 reg = <0x0000 0 0 0 0>; 220 ieee80211-freq-limit = <5000000 6000000>; 221 mediatek,mtd-eeprom = <&factory 0x8000>; 222 big-endian; 223 224 led { 225 led-sources = <2>; 226 }; 227 228 power-limits { 229 r0 { 230 regdomain = "FCC"; 231 txpower-5g { 232 b0 { 233 channels = <36 48>; 234 rates-ofdm = /bits/ 8 <23 23 23 23 23 23 23 23>; 235 rates-mcs = /bits/ 8 <1 23 23 23 23 23 23 23 23 23 23>, 236 /bits/ 8 <3 22 22 22 22 22 22 22 22 22 22>; 237 rates-ru = /bits/ 8 <3 22 22 22 22 22 22 22 22 22 22 22 22>, 238 /bits/ 8 <4 20 20 20 20 20 20 20 20 20 20 20 20>; 239 }; 240 b1 { 241 channels = <100 181>; 242 rates-ofdm = /bits/ 8 <14 14 14 14 14 14 14 14>; 243 rates-mcs = /bits/ 8 <4 14 14 14 14 14 14 14 14 14 14>; 244 txs-delta = <12 9 6>; 245 rates-ru = /bits/ 8 <7 14 14 14 14 14 14 14 14 14 14 14 14>; 246 }; 247 }; 248 }; 249 }; 250 }; 251 }; 252 253 - | 254 wifi@10300000 { 255 compatible = "mediatek,mt7628-wmac"; 256 reg = <0x10300000 0x100000>; 257 258 interrupt-parent = <&cpuintc>; 259 interrupts = <6>; 260 261 mediatek,mtd-eeprom = <&factory 0x0>; 262 }; 263 264 - | 265 #include <dt-bindings/interrupt-controller/arm-gic.h> 266 #include <dt-bindings/interrupt-controller/irq.h> 267 wifi@18000000 { 268 compatible = "mediatek,mt7622-wmac"; 269 reg = <0x10300000 0x100000>; 270 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>; 271 272 mediatek,infracfg = <&infracfg>; 273 274 power-domains = <&scpsys 3>; 275 }; 276 277 - | 278 wifi@18000000 { 279 compatible = "mediatek,mt7986-wmac"; 280 resets = <&watchdog 23>; 281 reset-names = "consys"; 282 reg = <0x18000000 0x1000000>, 283 <0x10003000 0x1000>, 284 <0x11d10000 0x1000>; 285 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&topckgen 50>, 287 <&topckgen 62>; 288 clock-names = "mcu", "ap2conn"; 289 memory-region = <&wmcpu_emi>; 290 }; 291