1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings 8 9maintainers: 10 - Grygorii Strashko <grygorii.strashko@ti.com> 11 - Sekhar Nori <nsekhar@ti.com> 12 13description: 14 The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports 15 (one external) and provides Ethernet packet communication for the device. 16 The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports 17 (two external) and provides Ethernet packet communication and switching. 18 19 The internal Communications Port Programming Interface (CPPI5) (Host port 0). 20 Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels 21 and one RX channels and operating by NAVSS Unified DMA Peripheral Root 22 Complex (UDMA-P) controller. 23 24 CPSWxG features 25 updated Address Lookup Engine (ALE). 26 priority level Quality Of Service (QOS) support (802.1p) 27 Support for Audio/Video Bridging (P802.1Qav/D6.0) 28 Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F) 29 Flow Control (802.3x) Support 30 Time Sensitive Network Support 31 IEEE P902.3br/D2.0 Interspersing Express Traffic 32 IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic 33 Configurable number of addresses plus VLANs 34 Configurable number of classifier/policers 35 VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on 36 ingress, Auto VLAN removal on egress and auto pad to minimum frame size. 37 RX/TX csum offload 38 Management Data Input/Output (MDIO) interface for PHYs management 39 RMII/RGMII Interfaces support 40 new version of Common Platform Time Sync (CPTS) 41 42 The CPSWxG NUSS is integrated into 43 device MCU domain named MCU_CPSW0 on AM654x/J721E SoC. 44 device MAIN domain named CPSW0 on AM642x SoC. 45 46 Specifications can be found at 47 https://www.ti.com/lit/pdf/spruid7 48 https://www.ti.com/lit/zip/spruil1 49 https://www.ti.com/lit/pdf/spruim2 50 51properties: 52 "#address-cells": true 53 "#size-cells": true 54 55 compatible: 56 enum: 57 - ti,am654-cpsw-nuss 58 - ti,j721e-cpsw-nuss 59 - ti,am642-cpsw-nuss 60 61 reg: 62 maxItems: 1 63 description: 64 The physical base address and size of full the CPSWxG NUSS IO range 65 66 reg-names: 67 items: 68 - const: cpsw_nuss 69 70 ranges: true 71 72 dma-coherent: true 73 74 clocks: 75 maxItems: 1 76 description: CPSWxG NUSS functional clock 77 78 clock-names: 79 items: 80 - const: fck 81 82 assigned-clock-parents: true 83 84 assigned-clocks: true 85 86 power-domains: 87 maxItems: 1 88 89 dmas: 90 maxItems: 9 91 92 dma-names: 93 items: 94 - const: tx0 95 - const: tx1 96 - const: tx2 97 - const: tx3 98 - const: tx4 99 - const: tx5 100 - const: tx6 101 - const: tx7 102 - const: rx 103 104 ethernet-ports: 105 type: object 106 properties: 107 '#address-cells': 108 const: 1 109 '#size-cells': 110 const: 0 111 112 patternProperties: 113 port@[1-2]: 114 type: object 115 description: CPSWxG NUSS external ports 116 117 $ref: ethernet-controller.yaml# 118 119 properties: 120 reg: 121 minimum: 1 122 maximum: 2 123 description: CPSW port number 124 125 phys: 126 maxItems: 1 127 description: phandle on phy-gmii-sel PHY 128 129 label: 130 description: label associated with this port 131 132 ti,mac-only: 133 $ref: /schemas/types.yaml#/definitions/flag 134 description: 135 Specifies the port works in mac-only mode. 136 137 ti,syscon-efuse: 138 $ref: /schemas/types.yaml#/definitions/phandle-array 139 items: 140 - items: 141 - description: Phandle to the system control device node which 142 provides access to efuse 143 - description: offset to efuse registers??? 144 description: 145 Phandle to the system control device node which provides access 146 to efuse IO range with MAC addresses 147 148 required: 149 - reg 150 - phys 151 152 additionalProperties: false 153 154patternProperties: 155 "^mdio@[0-9a-f]+$": 156 type: object 157 $ref: "ti,davinci-mdio.yaml#" 158 159 description: 160 CPSW MDIO bus. 161 162 "^cpts@[0-9a-f]+": 163 type: object 164 $ref: "ti,k3-am654-cpts.yaml#" 165 description: 166 CPSW Common Platform Time Sync (CPTS) module. 167 168required: 169 - compatible 170 - reg 171 - reg-names 172 - ranges 173 - clocks 174 - clock-names 175 - power-domains 176 - dmas 177 - dma-names 178 - '#address-cells' 179 - '#size-cells' 180 181additionalProperties: false 182 183examples: 184 - | 185 #include <dt-bindings/pinctrl/k3.h> 186 #include <dt-bindings/soc/ti,sci_pm_domain.h> 187 #include <dt-bindings/net/ti-dp83867.h> 188 #include <dt-bindings/interrupt-controller/irq.h> 189 #include <dt-bindings/interrupt-controller/arm-gic.h> 190 191 bus { 192 #address-cells = <2>; 193 #size-cells = <2>; 194 195 mcu_cpsw: ethernet@46000000 { 196 compatible = "ti,am654-cpsw-nuss"; 197 #address-cells = <2>; 198 #size-cells = <2>; 199 reg = <0x0 0x46000000 0x0 0x200000>; 200 reg-names = "cpsw_nuss"; 201 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 202 dma-coherent; 203 clocks = <&k3_clks 5 10>; 204 clock-names = "fck"; 205 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; 208 209 dmas = <&mcu_udmap 0xf000>, 210 <&mcu_udmap 0xf001>, 211 <&mcu_udmap 0xf002>, 212 <&mcu_udmap 0xf003>, 213 <&mcu_udmap 0xf004>, 214 <&mcu_udmap 0xf005>, 215 <&mcu_udmap 0xf006>, 216 <&mcu_udmap 0xf007>, 217 <&mcu_udmap 0x7000>; 218 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", 219 "rx"; 220 221 ethernet-ports { 222 #address-cells = <1>; 223 #size-cells = <0>; 224 225 cpsw_port1: port@1 { 226 reg = <1>; 227 ti,mac-only; 228 label = "port1"; 229 ti,syscon-efuse = <&mcu_conf 0x200>; 230 phys = <&phy_gmii_sel 1>; 231 232 phy-mode = "rgmii-rxid"; 233 phy-handle = <&phy0>; 234 }; 235 }; 236 237 davinci_mdio: mdio@f00 { 238 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 239 reg = <0x0 0xf00 0x0 0x100>; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 clocks = <&k3_clks 5 10>; 243 clock-names = "fck"; 244 bus_freq = <1000000>; 245 246 phy0: ethernet-phy@0 { 247 reg = <0>; 248 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 249 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 250 }; 251 }; 252 }; 253 254 cpts@3d000 { 255 compatible = "ti,am65-cpts"; 256 reg = <0x0 0x3d000 0x0 0x400>; 257 clocks = <&k3_clks 18 2>; 258 clock-names = "cpts"; 259 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 260 interrupt-names = "cpts"; 261 ti,cpts-ext-ts-inputs = <4>; 262 ti,cpts-periodic-outputs = <2>; 263 }; 264 }; 265