1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: TI SoC Ethernet Switch Controller (CPSW) Device Tree Bindings 8 9maintainers: 10 - Grygorii Strashko <grygorii.strashko@ti.com> 11 - Sekhar Nori <nsekhar@ti.com> 12 13description: 14 The 3-port switch gigabit ethernet subsystem provides ethernet packet 15 communication and can be configured as an ethernet switch. It provides the 16 gigabit media independent interface (GMII),reduced gigabit media 17 independent interface (RGMII), reduced media independent interface (RMII), 18 the management data input output (MDIO) for physical layer device (PHY) 19 management. 20 21properties: 22 compatible: 23 oneOf: 24 - const: ti,cpsw-switch 25 - items: 26 - const: ti,am335x-cpsw-switch 27 - const: ti,cpsw-switch 28 - items: 29 - const: ti,am4372-cpsw-switch 30 - const: ti,cpsw-switch 31 - items: 32 - const: ti,dra7-cpsw-switch 33 - const: ti,cpsw-switch 34 35 reg: 36 maxItems: 1 37 description: 38 The physical base address and size of full the CPSW module IO range 39 40 '#address-cells': 41 const: 1 42 43 '#size-cells': 44 const: 1 45 46 ranges: true 47 48 clocks: 49 maxItems: 1 50 description: CPSW functional clock 51 52 clock-names: 53 items: 54 - const: fck 55 56 interrupts: 57 items: 58 - description: RX_THRESH interrupt 59 - description: RX interrupt 60 - description: TX interrupt 61 - description: MISC interrupt 62 63 interrupt-names: 64 items: 65 - const: "rx_thresh" 66 - const: "rx" 67 - const: "tx" 68 - const: "misc" 69 70 pinctrl-names: true 71 72 syscon: 73 $ref: /schemas/types.yaml#/definitions/phandle 74 description: 75 Phandle to the system control device node which provides access to 76 efuse IO range with MAC addresses 77 78 ethernet-ports: 79 type: object 80 properties: 81 '#address-cells': 82 const: 1 83 '#size-cells': 84 const: 0 85 86 patternProperties: 87 "^port@[0-9]+$": 88 type: object 89 description: CPSW external ports 90 91 allOf: 92 - $ref: ethernet-controller.yaml# 93 94 properties: 95 reg: 96 items: 97 - enum: [1, 2] 98 description: CPSW port number 99 100 phys: 101 maxItems: 1 102 description: phandle on phy-gmii-sel PHY 103 104 label: 105 description: label associated with this port 106 107 ti,dual-emac-pvid: 108 $ref: /schemas/types.yaml#/definitions/uint32 109 minimum: 1 110 maximum: 1024 111 description: 112 Specifies default PORT VID to be used to segregate 113 ports. Default value - CPSW port number. 114 115 required: 116 - reg 117 - phys 118 119 cpts: 120 type: object 121 description: 122 The Common Platform Time Sync (CPTS) module 123 124 properties: 125 clocks: 126 maxItems: 1 127 description: CPTS reference clock 128 129 clock-names: 130 items: 131 - const: cpts 132 133 cpts_clock_mult: 134 $ref: /schemas/types.yaml#/definitions/uint32 135 description: 136 Numerator to convert input clock ticks into ns 137 138 cpts_clock_shift: 139 $ref: /schemas/types.yaml#/definitions/uint32 140 description: 141 Denominator to convert input clock ticks into ns. 142 Mult and shift will be calculated basing on CPTS rftclk frequency if 143 both cpts_clock_shift and cpts_clock_mult properties are not provided. 144 145 required: 146 - clocks 147 - clock-names 148 149patternProperties: 150 "^mdio@": 151 type: object 152 description: 153 CPSW MDIO bus. 154 $ref: "ti,davinci-mdio.yaml#" 155 156 157required: 158 - compatible 159 - reg 160 - ranges 161 - clocks 162 - clock-names 163 - interrupts 164 - interrupt-names 165 - '#address-cells' 166 - '#size-cells' 167 168additionalProperties: false 169 170examples: 171 - | 172 #include <dt-bindings/interrupt-controller/irq.h> 173 #include <dt-bindings/interrupt-controller/arm-gic.h> 174 #include <dt-bindings/clock/dra7.h> 175 176 mac_sw: switch@0 { 177 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch"; 178 reg = <0x0 0x4000>; 179 ranges = <0 0 0x4000>; 180 clocks = <&gmac_main_clk>; 181 clock-names = "fck"; 182 #address-cells = <1>; 183 #size-cells = <1>; 184 syscon = <&scm_conf>; 185 186 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 190 interrupt-names = "rx_thresh", "rx", "tx", "misc"; 191 192 ethernet-ports { 193 #address-cells = <1>; 194 #size-cells = <0>; 195 196 cpsw_port1: port@1 { 197 reg = <1>; 198 label = "port1"; 199 mac-address = [ 00 00 00 00 00 00 ]; 200 phys = <&phy_gmii_sel 1>; 201 phy-handle = <ðphy0_sw>; 202 phy-mode = "rgmii"; 203 ti,dual-emac-pvid = <1>; 204 }; 205 206 cpsw_port2: port@2 { 207 reg = <2>; 208 label = "wan"; 209 mac-address = [ 00 00 00 00 00 00 ]; 210 phys = <&phy_gmii_sel 2>; 211 phy-handle = <ðphy1_sw>; 212 phy-mode = "rgmii"; 213 ti,dual-emac-pvid = <2>; 214 }; 215 }; 216 217 davinci_mdio_sw: mdio@1000 { 218 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 219 reg = <0x1000 0x100>; 220 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; 221 clock-names = "fck"; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 bus_freq = <1000000>; 225 226 ethphy0_sw: ethernet-phy@0 { 227 reg = <0>; 228 }; 229 230 ethphy1_sw: ethernet-phy@1 { 231 reg = <1>; 232 }; 233 }; 234 235 cpts { 236 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; 237 clock-names = "cpts"; 238 }; 239 }; 240