xref: /freebsd/sys/contrib/device-tree/Bindings/net/pcs/mediatek,sgmiisys.yaml (revision 59c8e88e72633afbc47a4ace0d2170d00d51f7dc) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek SGMIISYS Controller
8
9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11
12description:
13  The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks
14  to the ethernet subsystem to which it is attached.
15
16properties:
17  compatible:
18    items:
19      - enum:
20          - mediatek,mt7622-sgmiisys
21          - mediatek,mt7629-sgmiisys
22          - mediatek,mt7981-sgmiisys_0
23          - mediatek,mt7981-sgmiisys_1
24          - mediatek,mt7986-sgmiisys_0
25          - mediatek,mt7986-sgmiisys_1
26      - const: syscon
27
28  reg:
29    maxItems: 1
30
31  '#clock-cells':
32    const: 1
33
34  mediatek,pnswap:
35    description: Invert polarity of the SGMII data lanes
36    type: boolean
37
38required:
39  - compatible
40  - reg
41  - '#clock-cells'
42
43additionalProperties: false
44
45examples:
46  - |
47    soc {
48      #address-cells = <2>;
49      #size-cells = <2>;
50      sgmiisys: syscon@1b128000 {
51        compatible = "mediatek,mt7622-sgmiisys", "syscon";
52        reg = <0 0x1b128000 0 0x1000>;
53        #clock-cells = <1>;
54      };
55    };
56