xref: /freebsd/sys/contrib/device-tree/Bindings/net/motorcomm,yt8xxx.yaml (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/motorcomm,yt8xxx.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MotorComm yt8xxx Ethernet PHY
8
9maintainers:
10  - Frank Sae <frank.sae@motor-comm.com>
11
12allOf:
13  - $ref: ethernet-phy.yaml#
14
15properties:
16  compatible:
17    enum:
18      - ethernet-phy-id4f51.e91a
19      - ethernet-phy-id4f51.e91b
20
21  rx-internal-delay-ps:
22    description: |
23      RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24      internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
25    enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650,
26            1800, 1900, 1950, 2050, 2100, 2200, 2250, 2350, 2500, 2650, 2800,
27            2950, 3100, 3250, 3400, 3550, 3700, 3850, 4000, 4150 ]
28    default: 1950
29
30  tx-internal-delay-ps:
31    description: |
32      RGMII TX Clock Delay used only when PHY operates in RGMII mode with
33      internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
34    enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, 1800,
35            1950, 2100, 2250 ]
36    default: 1950
37
38  motorcomm,clk-out-frequency-hz:
39    description: clock output on clock output pin.
40    enum: [0, 25000000, 125000000]
41    default: 0
42
43  motorcomm,keep-pll-enabled:
44    description: |
45      If set, keep the PLL enabled even if there is no link. Useful if you
46      want to use the clock output without an ethernet link.
47    type: boolean
48
49  motorcomm,auto-sleep-disabled:
50    description: |
51      If set, PHY will not enter sleep mode and close AFE after unplug cable
52      for a timer.
53    type: boolean
54
55  motorcomm,tx-clk-adj-enabled:
56    description: |
57      This configuration is mainly to adapt to VF2 with JH7110 SoC.
58      Useful if you want to use tx-clk-xxxx-inverted to adj the delay of tx clk.
59    type: boolean
60
61  motorcomm,tx-clk-10-inverted:
62    description: |
63      Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
64      Transmit PHY Clock delay train configuration when speed is 10Mbps.
65    type: boolean
66
67  motorcomm,tx-clk-100-inverted:
68    description: |
69      Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
70      Transmit PHY Clock delay train configuration when speed is 100Mbps.
71    type: boolean
72
73  motorcomm,tx-clk-1000-inverted:
74    description: |
75      Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
76      Transmit PHY Clock delay train configuration when speed is 1000Mbps.
77    type: boolean
78
79unevaluatedProperties: false
80
81examples:
82  - |
83    mdio {
84        #address-cells = <1>;
85        #size-cells = <0>;
86        phy-mode = "rgmii-id";
87        ethernet-phy@4 {
88            /*  Only needed to make DT lint tools work. Do not copy/paste
89             *  into real DTS files.
90             */
91            compatible = "ethernet-phy-id4f51.e91a";
92
93            reg = <4>;
94            rx-internal-delay-ps = <2100>;
95            tx-internal-delay-ps = <150>;
96            motorcomm,clk-out-frequency-hz = <0>;
97            motorcomm,keep-pll-enabled;
98            motorcomm,auto-sleep-disabled;
99        };
100    };
101  - |
102    mdio {
103        #address-cells = <1>;
104        #size-cells = <0>;
105        phy-mode = "rgmii";
106        ethernet-phy@5 {
107            /*  Only needed to make DT lint tools work. Do not copy/paste
108             *  into real DTS files.
109             */
110            compatible = "ethernet-phy-id4f51.e91a";
111
112            reg = <5>;
113            motorcomm,clk-out-frequency-hz = <125000000>;
114            motorcomm,keep-pll-enabled;
115            motorcomm,auto-sleep-disabled;
116        };
117    };
118