1MediaTek Frame Engine Ethernet controller 2========================================= 3 4The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs 5have dual GMAC each represented by a child node.. 6 7* Ethernet controller node 8 9Required properties: 10- compatible: Should be 11 "mediatek,mt2701-eth": for MT2701 SoC 12 "mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC 13 "mediatek,mt7622-eth": for MT7622 SoC 14 "mediatek,mt7629-eth": for MT7629 SoC 15 "ralink,rt5350-eth": for Ralink Rt5350F and MT7628/88 SoC 16- reg: Address and length of the register set for the device 17- interrupts: Should contain the three frame engines interrupts in numeric 18 order. These are fe_int0, fe_int1 and fe_int2. 19- clocks: the clock used by the core 20- clock-names: the names of the clock listed in the clocks property. These are 21 "ethif", "esw", "gp2", "gp1" : For MT2701 and MT7623 SoC 22 "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m", 23 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC 24 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "sgmii_tx250m", 25 "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii2_tx250m", 26 "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", "sgmii_ck", 27 "eth2pll" : For MT7629 SoC. 28- power-domains: phandle to the power domain that the ethernet is part of 29- resets: Should contain phandles to the ethsys reset signals 30- reset-names: Should contain the names of reset signal listed in the resets 31 property 32 These are "fe", "gmac" and "ppe" 33- mediatek,ethsys: phandle to the syscon node that handles the port setup 34- mediatek,infracfg: phandle to the syscon node that handles the path from 35 GMAC to PHY variants, which is required for MT7629 SoC. 36- mediatek,sgmiisys: a list of phandles to the syscon node that handles the 37 SGMII setup which is required for those SoCs equipped with SGMII such 38 as MT7622 and MT7629 SoC. And MT7622 have only one set of SGMII shared 39 by GMAC1 and GMAC2; MT7629 have two independent sets of SGMII directed 40 to GMAC1 and GMAC2, respectively. 41- mediatek,pctl: phandle to the syscon node that handles the ports slew rate 42 and driver current: only for MT2701 and MT7623 SoC 43 44* Ethernet MAC node 45 46Required properties: 47- compatible: Should be "mediatek,eth-mac" 48- reg: The number of the MAC 49- phy-handle: see ethernet.txt file in the same directory and 50 the phy-mode "trgmii" required being provided when reg 51 is equal to 0 and the MAC uses fixed-link to connect 52 with internal switch such as MT7530. 53 54Example: 55 56eth: ethernet@1b100000 { 57 compatible = "mediatek,mt7623-eth"; 58 reg = <0 0x1b100000 0 0x20000>; 59 clocks = <&topckgen CLK_TOP_ETHIF_SEL>, 60 <ðsys CLK_ETHSYS_ESW>, 61 <ðsys CLK_ETHSYS_GP2>, 62 <ðsys CLK_ETHSYS_GP1>; 63 clock-names = "ethif", "esw", "gp2", "gp1"; 64 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW 65 GIC_SPI 199 IRQ_TYPE_LEVEL_LOW 66 GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; 67 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; 68 resets = <ðsys MT2701_ETHSYS_ETH_RST>; 69 reset-names = "eth"; 70 mediatek,ethsys = <ðsys>; 71 mediatek,pctl = <&syscfg_pctl_a>; 72 #address-cells = <1>; 73 #size-cells = <0>; 74 75 gmac1: mac@0 { 76 compatible = "mediatek,eth-mac"; 77 reg = <0>; 78 phy-handle = <&phy0>; 79 }; 80 81 gmac2: mac@1 { 82 compatible = "mediatek,eth-mac"; 83 reg = <1>; 84 phy-handle = <&phy1>; 85 }; 86 87 mdio-bus { 88 phy0: ethernet-phy@0 { 89 reg = <0>; 90 phy-mode = "rgmii"; 91 }; 92 93 phy1: ethernet-phy@1 { 94 reg = <1>; 95 phy-mode = "rgmii"; 96 }; 97 }; 98}; 99