1Properties for an MDIO bus multiplexer controlled by a memory-mapped device 2 3This is a special case of a MDIO bus multiplexer. A memory-mapped device, 4like an FPGA, is used to control which child bus is connected. The mdio-mux 5node must be a child of the memory-mapped device. The driver currently only 6supports devices with 8, 16 or 32-bit registers. 7 8Required properties in addition to the generic multiplexer properties: 9 10- compatible : string, must contain "mdio-mux-mmioreg" 11 12- reg : integer, contains the offset of the register that controls the bus 13 multiplexer. The size field in the 'reg' property is the size of 14 register, and must therefore be 1, 2, or 4. 15 16- mux-mask : integer, contains an eight-bit mask that specifies which 17 bits in the register control the actual bus multiplexer. The 18 'reg' property of each child mdio-mux node must be constrained by 19 this mask. 20 21Example: 22 23The FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes. 24For the "EMI2" MDIO bus, register 9 (BRDCFG1) controls the mux on that bus. 25A bitmask of 0x6 means that bits 1 and 2 (bit 0 is lsb) are the bits on 26BRDCFG1 that control the actual mux. 27 28 /* The FPGA node */ 29 fpga: board-control@3,0 { 30 #address-cells = <1>; 31 #size-cells = <1>; 32 compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis"; 33 reg = <3 0 0x30>; 34 ranges = <0 3 0 0x30>; 35 36 mdio-mux-emi2 { 37 compatible = "mdio-mux-mmioreg", "mdio-mux"; 38 mdio-parent-bus = <&xmdio0>; 39 #address-cells = <1>; 40 #size-cells = <0>; 41 reg = <9 1>; // BRDCFG1 42 mux-mask = <0x6>; // EMI2 43 44 emi2_slot1: mdio@0 { // Slot 1 XAUI (FM2) 45 reg = <0>; 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 phy_xgmii_slot1: ethernet-phy@0 { 50 compatible = "ethernet-phy-ieee802.3-c45"; 51 reg = <4>; 52 }; 53 }; 54 55 emi2_slot2: mdio@2 { // Slot 2 XAUI (FM1) 56 reg = <2>; 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 phy_xgmii_slot2: ethernet-phy@4 { 61 compatible = "ethernet-phy-ieee802.3-c45"; 62 reg = <0>; 63 }; 64 }; 65 }; 66 }; 67 68 /* The parent MDIO bus. */ 69 xmdio0: mdio@f1000 { 70 #address-cells = <1>; 71 #size-cells = <0>; 72 compatible = "fsl,fman-xmdio"; 73 reg = <0xf1000 0x1000>; 74 interrupts = <100 1 0 0>; 75 }; 76