xref: /freebsd/sys/contrib/device-tree/Bindings/net/marvell,prestera.txt (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1Marvell Prestera Switch Chip bindings
2-------------------------------------
3
4Required properties:
5- compatible: must be "marvell,prestera" and one of the following
6	"marvell,prestera-98dx3236",
7	"marvell,prestera-98dx3336",
8	"marvell,prestera-98dx4251",
9- reg: address and length of the register set for the device.
10- interrupts: interrupt for the device
11
12Optional properties:
13- dfx: phandle reference to the "DFX Server" node
14
15Example:
16
17switch {
18	compatible = "simple-bus";
19	#address-cells = <1>;
20	#size-cells = <1>;
21	ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
22
23	packet-processor@0 {
24		compatible = "marvell,prestera-98dx3236", "marvell,prestera";
25		reg = <0 0x4000000>;
26		interrupts = <33>, <34>, <35>;
27		dfx = <&dfx>;
28	};
29};
30
31DFX Server bindings
32-------------------
33
34Required properties:
35- compatible: must be "marvell,dfx-server", "simple-bus"
36- ranges: describes the address mapping of a memory-mapped bus.
37- reg: address and length of the register set for the device.
38
39Example:
40
41dfx-server {
42	compatible = "marvell,dfx-server", "simple-bus";
43	#address-cells = <1>;
44	#size-cells = <1>;
45	ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
46	reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
47};
48
49Marvell Prestera SwitchDev bindings
50-----------------------------------
51Optional properties:
52- compatible: must be "marvell,prestera"
53- base-mac-provider: describes handle to node which provides base mac address,
54	might be a static base mac address or nvme cell provider.
55
56Example:
57
58eeprom_mac_addr: eeprom-mac-addr {
59       compatible = "eeprom,mac-addr-cell";
60       status = "okay";
61
62       nvmem = <&eeprom_at24>;
63};
64
65prestera {
66       compatible = "marvell,prestera";
67       status = "okay";
68
69       base-mac-provider = <&eeprom_mac_addr>;
70};
71
72The current implementation of Prestera Switchdev PCI interface driver requires
73that BAR2 is assigned to 0xf6000000 as base address from the PCI IO range:
74
75&cp0_pcie0 {
76	ranges = <0x81000000 0x0 0xfb000000 0x0 0xfb000000 0x0 0xf0000
77		0x82000000 0x0 0xf6000000 0x0 0xf6000000 0x0 0x2000000
78		0x82000000 0x0 0xf9000000 0x0 0xf9000000 0x0 0x100000>;
79	phys = <&cp0_comphy0 0>;
80	status = "okay";
81};
82