1============================================================================= 2Freescale Frame Manager Device Bindings 3 4CONTENTS 5 - FMan Node 6 - FMan Port Node 7 - FMan MURAM Node 8 - FMan dTSEC/XGEC/mEMAC Node 9 - FMan IEEE 1588 Node 10 - FMan MDIO Node 11 - Example 12 13============================================================================= 14FMan Node 15 16DESCRIPTION 17 18Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs, 19etc.) the FMan node will have child nodes for each of them. 20 21PROPERTIES 22 23- compatible 24 Usage: required 25 Value type: <stringlist> 26 Definition: Must include "fsl,fman" 27 FMan version can be determined via FM_IP_REV_1 register in the 28 FMan block. The offset is 0xc4 from the beginning of the 29 Frame Processing Manager memory map (0xc3000 from the 30 beginning of the FMan node). 31 32- cell-index 33 Usage: required 34 Value type: <u32> 35 Definition: Specifies the index of the FMan unit. 36 37 The cell-index value may be used by the SoC, to identify the 38 FMan unit in the SoC memory map. In the table below, 39 there's a description of the cell-index use in each SoC: 40 41 - P1023: 42 register[bit] FMan unit cell-index 43 ============================================================ 44 DEVDISR[1] 1 0 45 46 - P2041, P3041, P4080 P5020, P5040: 47 register[bit] FMan unit cell-index 48 ============================================================ 49 DCFG_DEVDISR2[6] 1 0 50 DCFG_DEVDISR2[14] 2 1 51 (Second FM available only in P4080 and P5040) 52 53 - B4860, T1040, T2080, T4240: 54 register[bit] FMan unit cell-index 55 ============================================================ 56 DCFG_CCSR_DEVDISR2[24] 1 0 57 DCFG_CCSR_DEVDISR2[25] 2 1 58 (Second FM available only in T4240) 59 60 DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in 61 the specific SoC "Device Configuration/Pin Control" Memory 62 Map. 63 64- reg 65 Usage: required 66 Value type: <prop-encoded-array> 67 Definition: A standard property. Specifies the offset of the 68 following configuration registers: 69 - BMI configuration registers. 70 - QMI configuration registers. 71 - DMA configuration registers. 72 - FPM configuration registers. 73 - FMan controller configuration registers. 74 75- ranges 76 Usage: required 77 Value type: <prop-encoded-array> 78 Definition: A standard property. 79 80- clocks 81 Usage: required 82 Value type: <prop-encoded-array> 83 Definition: phandle for the fman input clock. 84 85- clock-names 86 usage: required 87 Value type: <stringlist> 88 Definition: "fmanclk" for the fman input clock. 89 90- interrupts 91 Usage: required 92 Value type: <prop-encoded-array> 93 Definition: A pair of IRQs are specified in this property. 94 The first element is associated with the event interrupts and 95 the second element is associated with the error interrupts. 96 97- fsl,qman-channel-range 98 Usage: required 99 Value type: <prop-encoded-array> 100 Definition: Specifies the range of the available dedicated 101 channels in the FMan. The first cell specifies the beginning 102 of the range and the second cell specifies the number of 103 channels. 104 Further information available at: 105 "Work Queue (WQ) Channel Assignments in the QMan" section 106 in DPAA Reference Manual. 107 108- fsl,qman 109- fsl,bman 110 Usage: required 111 Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt 112 113- fsl,erratum-a050385 114 Usage: optional 115 Value type: boolean 116 Definition: A boolean property. Indicates the presence of the 117 erratum A050385 which indicates that DMA transactions that are 118 split can result in a FMan lock. 119 120============================================================================= 121FMan MURAM Node 122 123DESCRIPTION 124 125FMan Internal memory - shared between all the FMan modules. 126It contains data structures that are common and written to or read by 127the modules. 128FMan internal memory is split into the following parts: 129 Packet buffering (Tx/Rx FIFOs) 130 Frames internal context 131 132PROPERTIES 133 134- compatible 135 Usage: required 136 Value type: <stringlist> 137 Definition: Must include "fsl,fman-muram" 138 139- ranges 140 Usage: required 141 Value type: <prop-encoded-array> 142 Definition: A standard property. 143 Specifies the multi-user memory offset and the size within 144 the FMan. 145 146EXAMPLE 147 148muram@0 { 149 compatible = "fsl,fman-muram"; 150 ranges = <0 0x000000 0x28000>; 151}; 152 153============================================================================= 154FMan Port Node 155 156DESCRIPTION 157 158The Frame Manager (FMan) supports several types of hardware ports: 159 Ethernet receiver (RX) 160 Ethernet transmitter (TX) 161 Offline/Host command (O/H) 162 163PROPERTIES 164 165- compatible 166 Usage: required 167 Value type: <stringlist> 168 Definition: A standard property. 169 Must include one of the following: 170 - "fsl,fman-v2-port-oh" for FManV2 OH ports 171 - "fsl,fman-v2-port-rx" for FManV2 RX ports 172 - "fsl,fman-v2-port-tx" for FManV2 TX ports 173 - "fsl,fman-v3-port-oh" for FManV3 OH ports 174 - "fsl,fman-v3-port-rx" for FManV3 RX ports 175 - "fsl,fman-v3-port-tx" for FManV3 TX ports 176 177- cell-index 178 Usage: required 179 Value type: <u32> 180 Definition: Specifies the hardware port id. 181 Each hardware port on the FMan has its own hardware PortID. 182 Super set of all hardware Port IDs available at FMan Reference 183 Manual under "FMan Hardware Ports in Freescale Devices" table. 184 185 Each hardware port is assigned a 4KB, port-specific page in 186 the FMan hardware port memory region (which is part of the 187 FMan memory map). The first 4 KB in the FMan hardware ports 188 memory region is used for what are called common registers. 189 The subsequent 63 4KB pages are allocated to the hardware 190 ports. 191 The page of a specific port is determined by the cell-index. 192 193- reg 194 Usage: required 195 Value type: <prop-encoded-array> 196 Definition: There is one reg region describing the port 197 configuration registers. 198 199- fsl,fman-10g-port 200 Usage: optional 201 Value type: boolean 202 Definition: The default port rate is 1G. 203 If this property exists, the port is s 10G port. 204 205- fsl,fman-best-effort-port 206 Usage: optional 207 Value type: boolean 208 Definition: Can be defined only if 10G-support is set. 209 This property marks a best-effort 10G port (10G port that 210 may not be capable of line rate). 211 212EXAMPLE 213 214port@a8000 { 215 cell-index = <0x28>; 216 compatible = "fsl,fman-v2-port-tx"; 217 reg = <0xa8000 0x1000>; 218}; 219 220port@88000 { 221 cell-index = <0x8>; 222 compatible = "fsl,fman-v2-port-rx"; 223 reg = <0x88000 0x1000>; 224}; 225 226port@81000 { 227 cell-index = <0x1>; 228 compatible = "fsl,fman-v2-port-oh"; 229 reg = <0x81000 0x1000>; 230}; 231 232============================================================================= 233FMan dTSEC/XGEC/mEMAC Node 234 235DESCRIPTION 236 237mEMAC/dTSEC/XGEC are the Ethernet network interfaces 238 239PROPERTIES 240 241- compatible 242 Usage: required 243 Value type: <stringlist> 244 Definition: A standard property. 245 Must include one of the following: 246 - "fsl,fman-dtsec" for dTSEC MAC 247 - "fsl,fman-xgec" for XGEC MAC 248 - "fsl,fman-memac" for mEMAC MAC 249 250- cell-index 251 Usage: required 252 Value type: <u32> 253 Definition: Specifies the MAC id. 254 255 The cell-index value may be used by the FMan or the SoC, to 256 identify the MAC unit in the FMan (or SoC) memory map. 257 In the tables below there's a description of the cell-index 258 use, there are two tables, one describes the use of cell-index 259 by the FMan, the second describes the use by the SoC: 260 261 1. FMan Registers 262 263 FManV2: 264 register[bit] MAC cell-index 265 ============================================================ 266 FM_EPI[16] XGEC 8 267 FM_EPI[16+n] dTSECn n-1 268 FM_NPI[11+n] dTSECn n-1 269 n = 1,..,5 270 271 FManV3: 272 register[bit] MAC cell-index 273 ============================================================ 274 FM_EPI[16+n] mEMACn n-1 275 FM_EPI[25] mEMAC10 9 276 277 FM_NPI[11+n] mEMACn n-1 278 FM_NPI[10] mEMAC10 9 279 FM_NPI[11] mEMAC9 8 280 n = 1,..8 281 282 FM_EPI and FM_NPI are located in the FMan memory map. 283 284 2. SoC registers: 285 286 - P2041, P3041, P4080 P5020, P5040: 287 register[bit] FMan MAC cell 288 Unit index 289 ============================================================ 290 DCFG_DEVDISR2[7] 1 XGEC 8 291 DCFG_DEVDISR2[7+n] 1 dTSECn n-1 292 DCFG_DEVDISR2[15] 2 XGEC 8 293 DCFG_DEVDISR2[15+n] 2 dTSECn n-1 294 n = 1,..5 295 296 - T1040, T2080, T4240, B4860: 297 register[bit] FMan MAC cell 298 Unit index 299 ============================================================ 300 DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1 301 DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1 302 n = 1,..6,9,10 303 304 EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in 305 the specific SoC "Device Configuration/Pin Control" Memory 306 Map. 307 308- reg 309 Usage: required 310 Value type: <prop-encoded-array> 311 Definition: A standard property. 312 313- fsl,fman-ports 314 Usage: required 315 Value type: <prop-encoded-array> 316 Definition: An array of two phandles - the first references is 317 the FMan RX port and the second is the TX port used by this 318 MAC. 319 320- ptp-timer 321 Usage required 322 Value type: <phandle> 323 Definition: A phandle for 1EEE1588 timer. 324 325- pcsphy-handle 326 Usage required for "fsl,fman-memac" MACs 327 Value type: <phandle> 328 Definition: A phandle for pcsphy. 329 330- tbi-handle 331 Usage required for "fsl,fman-dtsec" MACs 332 Value type: <phandle> 333 Definition: A phandle for tbiphy. 334 335EXAMPLE 336 337fman1_tx28: port@a8000 { 338 cell-index = <0x28>; 339 compatible = "fsl,fman-v2-port-tx"; 340 reg = <0xa8000 0x1000>; 341}; 342 343fman1_rx8: port@88000 { 344 cell-index = <0x8>; 345 compatible = "fsl,fman-v2-port-rx"; 346 reg = <0x88000 0x1000>; 347}; 348 349ptp-timer: ptp_timer@fe000 { 350 compatible = "fsl,fman-ptp-timer"; 351 reg = <0xfe000 0x1000>; 352}; 353 354ethernet@e0000 { 355 compatible = "fsl,fman-dtsec"; 356 cell-index = <0>; 357 reg = <0xe0000 0x1000>; 358 fsl,fman-ports = <&fman1_rx8 &fman1_tx28>; 359 ptp-timer = <&ptp-timer>; 360 tbi-handle = <&tbi0>; 361}; 362 363============================================================================ 364FMan IEEE 1588 Node 365 366Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt 367 368============================================================================= 369FMan MDIO Node 370 371DESCRIPTION 372 373The MDIO is a bus to which the PHY devices are connected. 374 375PROPERTIES 376 377- compatible 378 Usage: required 379 Value type: <stringlist> 380 Definition: A standard property. 381 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2. 382 Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2. 383 Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from 384 FMan v3. 385 386- reg 387 Usage: required 388 Value type: <prop-encoded-array> 389 Definition: A standard property. 390 391- bus-frequency 392 Usage: optional 393 Value type: <u32> 394 Definition: Specifies the external MDIO bus clock speed to 395 be used, if different from the standard 2.5 MHz. 396 This may be due to the standard speed being unsupported (e.g. 397 due to a hardware problem), or to advertise that all relevant 398 components in the system support a faster speed. 399 400- interrupts 401 Usage: required for external MDIO 402 Value type: <prop-encoded-array> 403 Definition: Event interrupt of external MDIO controller. 404 405- fsl,fman-internal-mdio 406 Usage: required for internal MDIO 407 Value type: boolean 408 Definition: Fman has internal MDIO for internal PCS(Physical 409 Coding Sublayer) PHYs and external MDIO for external PHYs. 410 The settings and programming routines for internal/external 411 MDIO are different. Must be included for internal MDIO. 412 413- fsl,erratum-a011043 414 Usage: optional 415 Value type: <boolean> 416 Definition: Indicates the presence of the A011043 erratum 417 describing that the MDIO_CFG[MDIO_RD_ER] bit may be falsely 418 set when reading internal PCS registers. MDIO reads to 419 internal PCS registers may result in having the 420 MDIO_CFG[MDIO_RD_ER] bit set, even when there is no error and 421 read data (MDIO_DATA[MDIO_DATA]) is correct. 422 Software may get false read error when reading internal 423 PCS registers through MDIO. As a workaround, all internal 424 MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit. 425 426For internal PHY device on internal mdio bus, a PHY node should be created. 427See the definition of the PHY node in booting-without-of.txt for an 428example of how to define a PHY (Internal PHY has no interrupt line). 429- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY. 430- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY, 431 PCS PHY addr must be '0'. 432 433EXAMPLE 434 435Example for FMan v2 external MDIO: 436 437mdio@f1000 { 438 compatible = "fsl,fman-xmdio"; 439 reg = <0xf1000 0x1000>; 440 interrupts = <101 2 0 0>; 441}; 442 443Example for FMan v2 internal MDIO: 444 445mdio@e3120 { 446 compatible = "fsl,fman-mdio"; 447 reg = <0xe3120 0xee0>; 448 fsl,fman-internal-mdio; 449 450 tbi1: tbi-phy@8 { 451 reg = <0x8>; 452 device_type = "tbi-phy"; 453 }; 454}; 455 456Example for FMan v3 internal MDIO: 457 458mdio@f1000 { 459 compatible = "fsl,fman-memac-mdio"; 460 reg = <0xf1000 0x1000>; 461 fsl,fman-internal-mdio; 462 463 pcsphy6: ethernet-phy@0 { 464 reg = <0x0>; 465 }; 466}; 467 468============================================================================= 469Example 470 471fman@400000 { 472 #address-cells = <1>; 473 #size-cells = <1>; 474 cell-index = <1>; 475 compatible = "fsl,fman" 476 ranges = <0 0x400000 0x100000>; 477 reg = <0x400000 0x100000>; 478 clocks = <&fman_clk>; 479 clock-names = "fmanclk"; 480 interrupts = < 481 96 2 0 0 482 16 2 1 1>; 483 fsl,qman-channel-range = <0x40 0xc>; 484 485 muram@0 { 486 compatible = "fsl,fman-muram"; 487 reg = <0x0 0x28000>; 488 }; 489 490 port@81000 { 491 cell-index = <1>; 492 compatible = "fsl,fman-v2-port-oh"; 493 reg = <0x81000 0x1000>; 494 }; 495 496 port@82000 { 497 cell-index = <2>; 498 compatible = "fsl,fman-v2-port-oh"; 499 reg = <0x82000 0x1000>; 500 }; 501 502 port@83000 { 503 cell-index = <3>; 504 compatible = "fsl,fman-v2-port-oh"; 505 reg = <0x83000 0x1000>; 506 }; 507 508 port@84000 { 509 cell-index = <4>; 510 compatible = "fsl,fman-v2-port-oh"; 511 reg = <0x84000 0x1000>; 512 }; 513 514 port@85000 { 515 cell-index = <5>; 516 compatible = "fsl,fman-v2-port-oh"; 517 reg = <0x85000 0x1000>; 518 }; 519 520 port@86000 { 521 cell-index = <6>; 522 compatible = "fsl,fman-v2-port-oh"; 523 reg = <0x86000 0x1000>; 524 }; 525 526 fman1_rx_0x8: port@88000 { 527 cell-index = <0x8>; 528 compatible = "fsl,fman-v2-port-rx"; 529 reg = <0x88000 0x1000>; 530 }; 531 532 fman1_rx_0x9: port@89000 { 533 cell-index = <0x9>; 534 compatible = "fsl,fman-v2-port-rx"; 535 reg = <0x89000 0x1000>; 536 }; 537 538 fman1_rx_0xa: port@8a000 { 539 cell-index = <0xa>; 540 compatible = "fsl,fman-v2-port-rx"; 541 reg = <0x8a000 0x1000>; 542 }; 543 544 fman1_rx_0xb: port@8b000 { 545 cell-index = <0xb>; 546 compatible = "fsl,fman-v2-port-rx"; 547 reg = <0x8b000 0x1000>; 548 }; 549 550 fman1_rx_0xc: port@8c000 { 551 cell-index = <0xc>; 552 compatible = "fsl,fman-v2-port-rx"; 553 reg = <0x8c000 0x1000>; 554 }; 555 556 fman1_rx_0x10: port@90000 { 557 cell-index = <0x10>; 558 compatible = "fsl,fman-v2-port-rx"; 559 reg = <0x90000 0x1000>; 560 }; 561 562 fman1_tx_0x28: port@a8000 { 563 cell-index = <0x28>; 564 compatible = "fsl,fman-v2-port-tx"; 565 reg = <0xa8000 0x1000>; 566 }; 567 568 fman1_tx_0x29: port@a9000 { 569 cell-index = <0x29>; 570 compatible = "fsl,fman-v2-port-tx"; 571 reg = <0xa9000 0x1000>; 572 }; 573 574 fman1_tx_0x2a: port@aa000 { 575 cell-index = <0x2a>; 576 compatible = "fsl,fman-v2-port-tx"; 577 reg = <0xaa000 0x1000>; 578 }; 579 580 fman1_tx_0x2b: port@ab000 { 581 cell-index = <0x2b>; 582 compatible = "fsl,fman-v2-port-tx"; 583 reg = <0xab000 0x1000>; 584 }; 585 586 fman1_tx_0x2c: port@ac0000 { 587 cell-index = <0x2c>; 588 compatible = "fsl,fman-v2-port-tx"; 589 reg = <0xac000 0x1000>; 590 }; 591 592 fman1_tx_0x30: port@b0000 { 593 cell-index = <0x30>; 594 compatible = "fsl,fman-v2-port-tx"; 595 reg = <0xb0000 0x1000>; 596 }; 597 598 ethernet@e0000 { 599 compatible = "fsl,fman-dtsec"; 600 cell-index = <0>; 601 reg = <0xe0000 0x1000>; 602 fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>; 603 tbi-handle = <&tbi5>; 604 }; 605 606 ethernet@e2000 { 607 compatible = "fsl,fman-dtsec"; 608 cell-index = <1>; 609 reg = <0xe2000 0x1000>; 610 fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>; 611 tbi-handle = <&tbi6>; 612 }; 613 614 ethernet@e4000 { 615 compatible = "fsl,fman-dtsec"; 616 cell-index = <2>; 617 reg = <0xe4000 0x1000>; 618 fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>; 619 tbi-handle = <&tbi7>; 620 }; 621 622 ethernet@e6000 { 623 compatible = "fsl,fman-dtsec"; 624 cell-index = <3>; 625 reg = <0xe6000 0x1000>; 626 fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>; 627 tbi-handle = <&tbi8>; 628 }; 629 630 ethernet@e8000 { 631 compatible = "fsl,fman-dtsec"; 632 cell-index = <4>; 633 reg = <0xf0000 0x1000>; 634 fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>; 635 tbi-handle = <&tbi9>; 636 637 ethernet@f0000 { 638 cell-index = <8>; 639 compatible = "fsl,fman-xgec"; 640 reg = <0xf0000 0x1000>; 641 fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>; 642 }; 643 644 ptp-timer@fe000 { 645 compatible = "fsl,fman-ptp-timer"; 646 reg = <0xfe000 0x1000>; 647 }; 648 649 mdio@f1000 { 650 compatible = "fsl,fman-xmdio"; 651 reg = <0xf1000 0x1000>; 652 interrupts = <101 2 0 0>; 653 }; 654}; 655