1NXP SJA1105 switch driver 2========================= 3 4Required properties: 5 6- compatible: 7 Must be one of: 8 - "nxp,sja1105e" 9 - "nxp,sja1105t" 10 - "nxp,sja1105p" 11 - "nxp,sja1105q" 12 - "nxp,sja1105r" 13 - "nxp,sja1105s" 14 15 Although the device ID could be detected at runtime, explicit bindings 16 are required in order to be able to statically check their validity. 17 For example, SGMII can only be specified on port 4 of R and S devices, 18 and the non-SGMII devices, while pin-compatible, are not equal in terms 19 of support for RGMII internal delays (supported on P/Q/R/S, but not on 20 E/T). 21 22Optional properties: 23 24- sja1105,role-mac: 25- sja1105,role-phy: 26 Boolean properties that can be assigned under each port node. By 27 default (unless otherwise specified) a port is configured as MAC if it 28 is driving a PHY (phy-handle is present) or as PHY if it is PHY-less 29 (fixed-link specified, presumably because it is connected to a MAC). 30 The effect of this property (in either its implicit or explicit form) 31 is: 32 - In the case of MII or RMII it specifies whether the SJA1105 port is a 33 clock source or sink for this interface (not applicable for RGMII 34 where there is a Tx and an Rx clock). 35 - In the case of RGMII it affects the behavior regarding internal 36 delays: 37 1. If sja1105,role-mac is specified, and the phy-mode property is one 38 of "rgmii-id", "rgmii-txid" or "rgmii-rxid", then the entity 39 designated to apply the delay/clock skew necessary for RGMII 40 is the PHY. The SJA1105 MAC does not apply any internal delays. 41 2. If sja1105,role-phy is specified, and the phy-mode property is one 42 of the above, the designated entity to apply the internal delays 43 is the SJA1105 MAC (if hardware-supported). This is only supported 44 by the second-generation (P/Q/R/S) hardware. On a first-generation 45 E or T device, it is an error to specify an RGMII phy-mode other 46 than "rgmii" for a port that is in fixed-link mode. In that case, 47 the clock skew must either be added by the MAC at the other end of 48 the fixed-link, or by PCB serpentine traces on the board. 49 These properties are required, for example, in the case where SJA1105 50 ports are at both ends of a MII/RMII PHY-less setup. One end would need 51 to have sja1105,role-mac, while the other sja1105,role-phy. 52 53See Documentation/devicetree/bindings/net/dsa/dsa.txt for the list of standard 54DSA required and optional properties. 55 56Other observations 57------------------ 58 59The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944) of at least 60one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum 61cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed 62depends on the SPI bus master driver. 63 64Example 65------- 66 67Ethernet switch connected via SPI to the host, CPU port wired to enet2: 68 69arch/arm/boot/dts/ls1021a-tsn.dts: 70 71/* SPI controller of the LS1021 */ 72&dspi0 { 73 sja1105@1 { 74 reg = <0x1>; 75 #address-cells = <1>; 76 #size-cells = <0>; 77 compatible = "nxp,sja1105t"; 78 spi-max-frequency = <4000000>; 79 fsl,spi-cs-sck-delay = <1000>; 80 fsl,spi-sck-cs-delay = <1000>; 81 ports { 82 #address-cells = <1>; 83 #size-cells = <0>; 84 port@0 { 85 /* ETH5 written on chassis */ 86 label = "swp5"; 87 phy-handle = <&rgmii_phy6>; 88 phy-mode = "rgmii-id"; 89 reg = <0>; 90 /* Implicit "sja1105,role-mac;" */ 91 }; 92 port@1 { 93 /* ETH2 written on chassis */ 94 label = "swp2"; 95 phy-handle = <&rgmii_phy3>; 96 phy-mode = "rgmii-id"; 97 reg = <1>; 98 /* Implicit "sja1105,role-mac;" */ 99 }; 100 port@2 { 101 /* ETH3 written on chassis */ 102 label = "swp3"; 103 phy-handle = <&rgmii_phy4>; 104 phy-mode = "rgmii-id"; 105 reg = <2>; 106 /* Implicit "sja1105,role-mac;" */ 107 }; 108 port@3 { 109 /* ETH4 written on chassis */ 110 phy-handle = <&rgmii_phy5>; 111 label = "swp4"; 112 phy-mode = "rgmii-id"; 113 reg = <3>; 114 /* Implicit "sja1105,role-mac;" */ 115 }; 116 port@4 { 117 /* Internal port connected to eth2 */ 118 ethernet = <&enet2>; 119 phy-mode = "rgmii"; 120 reg = <4>; 121 /* Implicit "sja1105,role-phy;" */ 122 fixed-link { 123 speed = <1000>; 124 full-duplex; 125 }; 126 }; 127 }; 128 }; 129}; 130 131/* MDIO controller of the LS1021 */ 132&mdio0 { 133 /* BCM5464 */ 134 rgmii_phy3: ethernet-phy@3 { 135 reg = <0x3>; 136 }; 137 rgmii_phy4: ethernet-phy@4 { 138 reg = <0x4>; 139 }; 140 rgmii_phy5: ethernet-phy@5 { 141 reg = <0x5>; 142 }; 143 rgmii_phy6: ethernet-phy@6 { 144 reg = <0x6>; 145 }; 146}; 147 148/* Ethernet master port of the LS1021 */ 149&enet2 { 150 phy-connection-type = "rgmii"; 151 status = "ok"; 152 fixed-link { 153 speed = <1000>; 154 full-duplex; 155 }; 156}; 157