1Realtek SMI-based Switches 2========================== 3 4The SMI "Simple Management Interface" is a two-wire protocol using 5bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does 6not use the MDIO protocol. This binding defines how to specify the 7SMI-based Realtek devices. 8 9Required properties: 10 11- compatible: must be exactly one of: 12 "realtek,rtl8366" 13 "realtek,rtl8366rb" (4+1 ports) 14 "realtek,rtl8366s" (4+1 ports) 15 "realtek,rtl8367" 16 "realtek,rtl8367b" 17 "realtek,rtl8368s" (8 port) 18 "realtek,rtl8369" 19 "realtek,rtl8370" (8 port) 20 21Required properties: 22- mdc-gpios: GPIO line for the MDC clock line. 23- mdio-gpios: GPIO line for the MDIO data line. 24- reset-gpios: GPIO line for the reset signal. 25 26Optional properties: 27- realtek,disable-leds: if the LED drivers are not used in the 28 hardware design this will disable them so they are not turned on 29 and wasting power. 30 31Required subnodes: 32 33- interrupt-controller 34 35 This defines an interrupt controller with an IRQ line (typically 36 a GPIO) that will demultiplex and handle the interrupt from the single 37 interrupt line coming out of one of the SMI-based chips. It most 38 importantly provides link up/down interrupts to the PHY blocks inside 39 the ASIC. 40 41Required properties of interrupt-controller: 42 43- interrupt: parent interrupt, see interrupt-controller/interrupts.txt 44- interrupt-controller: see interrupt-controller/interrupts.txt 45- #address-cells: should be <0> 46- #interrupt-cells: should be <1> 47 48- mdio 49 50 This defines the internal MDIO bus of the SMI device, mostly for the 51 purpose of being able to hook the interrupts to the right PHY and 52 the right PHY to the corresponding port. 53 54Required properties of mdio: 55 56- compatible: should be set to "realtek,smi-mdio" for all SMI devices 57 58See net/mdio.txt for additional MDIO bus properties. 59 60See net/dsa/dsa.txt for a list of additional required and optional properties 61and subnodes of DSA switches. 62 63Examples: 64 65switch { 66 compatible = "realtek,rtl8366rb"; 67 /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ 68 mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; 69 mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; 70 reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; 71 72 switch_intc: interrupt-controller { 73 /* GPIO 15 provides the interrupt */ 74 interrupt-parent = <&gpio0>; 75 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 76 interrupt-controller; 77 #address-cells = <0>; 78 #interrupt-cells = <1>; 79 }; 80 81 ports { 82 #address-cells = <1>; 83 #size-cells = <0>; 84 reg = <0>; 85 port@0 { 86 reg = <0>; 87 label = "lan0"; 88 phy-handle = <&phy0>; 89 }; 90 port@1 { 91 reg = <1>; 92 label = "lan1"; 93 phy-handle = <&phy1>; 94 }; 95 port@2 { 96 reg = <2>; 97 label = "lan2"; 98 phy-handle = <&phy2>; 99 }; 100 port@3 { 101 reg = <3>; 102 label = "lan3"; 103 phy-handle = <&phy3>; 104 }; 105 port@4 { 106 reg = <4>; 107 label = "wan"; 108 phy-handle = <&phy4>; 109 }; 110 port@5 { 111 reg = <5>; 112 label = "cpu"; 113 ethernet = <&gmac0>; 114 phy-mode = "rgmii"; 115 fixed-link { 116 speed = <1000>; 117 full-duplex; 118 }; 119 }; 120 }; 121 122 mdio { 123 compatible = "realtek,smi-mdio", "dsa-mdio"; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 127 phy0: phy@0 { 128 reg = <0>; 129 interrupt-parent = <&switch_intc>; 130 interrupts = <0>; 131 }; 132 phy1: phy@1 { 133 reg = <1>; 134 interrupt-parent = <&switch_intc>; 135 interrupts = <1>; 136 }; 137 phy2: phy@2 { 138 reg = <2>; 139 interrupt-parent = <&switch_intc>; 140 interrupts = <2>; 141 }; 142 phy3: phy@3 { 143 reg = <3>; 144 interrupt-parent = <&switch_intc>; 145 interrupts = <3>; 146 }; 147 phy4: phy@4 { 148 reg = <4>; 149 interrupt-parent = <&switch_intc>; 150 interrupts = <12>; 151 }; 152 }; 153}; 154