1* Qualcomm Atheros QCA8xxx switch family 2 3Required properties: 4 5- compatible: should be one of: 6 "qca,qca8334" 7 "qca,qca8337" 8 9- #size-cells: must be 0 10- #address-cells: must be 1 11 12Optional properties: 13 14- reset-gpios: GPIO to be used to reset the whole device 15 16Subnodes: 17 18The integrated switch subnode should be specified according to the binding 19described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external 20mdio-bus each subnode describing a port needs to have a valid phandle 21referencing the internal PHY it is connected to. This is because there's no 22N:N mapping of port and PHY id. 23 24Don't use mixed external and internal mdio-bus configurations, as this is 25not supported by the hardware. 26 27The CPU port of this switch is always port 0. 28 29A CPU port node has the following optional node: 30 31- fixed-link : Fixed-link subnode describing a link to a non-MDIO 32 managed entity. See 33 Documentation/devicetree/bindings/net/fixed-link.txt 34 for details. 35 36For QCA8K the 'fixed-link' sub-node supports only the following properties: 37 38- 'speed' (integer, mandatory), to indicate the link speed. Accepted 39 values are 10, 100 and 1000 40- 'full-duplex' (boolean, optional), to indicate that full duplex is 41 used. When absent, half duplex is assumed. 42 43Examples: 44 45for the external mdio-bus configuration: 46 47 &mdio0 { 48 phy_port1: phy@0 { 49 reg = <0>; 50 }; 51 52 phy_port2: phy@1 { 53 reg = <1>; 54 }; 55 56 phy_port3: phy@2 { 57 reg = <2>; 58 }; 59 60 phy_port4: phy@3 { 61 reg = <3>; 62 }; 63 64 phy_port5: phy@4 { 65 reg = <4>; 66 }; 67 68 switch@10 { 69 compatible = "qca,qca8337"; 70 #address-cells = <1>; 71 #size-cells = <0>; 72 73 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; 74 reg = <0x10>; 75 76 ports { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 port@0 { 80 reg = <0>; 81 label = "cpu"; 82 ethernet = <&gmac1>; 83 phy-mode = "rgmii"; 84 fixed-link { 85 speed = 1000; 86 full-duplex; 87 }; 88 }; 89 90 port@1 { 91 reg = <1>; 92 label = "lan1"; 93 phy-handle = <&phy_port1>; 94 }; 95 96 port@2 { 97 reg = <2>; 98 label = "lan2"; 99 phy-handle = <&phy_port2>; 100 }; 101 102 port@3 { 103 reg = <3>; 104 label = "lan3"; 105 phy-handle = <&phy_port3>; 106 }; 107 108 port@4 { 109 reg = <4>; 110 label = "lan4"; 111 phy-handle = <&phy_port4>; 112 }; 113 114 port@5 { 115 reg = <5>; 116 label = "wan"; 117 phy-handle = <&phy_port5>; 118 }; 119 }; 120 }; 121 }; 122 123for the internal master mdio-bus configuration: 124 125 &mdio0 { 126 switch@10 { 127 compatible = "qca,qca8337"; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 131 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; 132 reg = <0x10>; 133 134 ports { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 port@0 { 139 reg = <0>; 140 label = "cpu"; 141 ethernet = <&gmac1>; 142 phy-mode = "rgmii"; 143 fixed-link { 144 speed = 1000; 145 full-duplex; 146 }; 147 }; 148 149 port@1 { 150 reg = <1>; 151 label = "lan1"; 152 }; 153 154 port@2 { 155 reg = <2>; 156 label = "lan2"; 157 }; 158 159 port@3 { 160 reg = <3>; 161 label = "lan3"; 162 }; 163 164 port@4 { 165 reg = <4>; 166 label = "lan4"; 167 }; 168 169 port@5 { 170 reg = <5>; 171 label = "wan"; 172 }; 173 }; 174 }; 175 }; 176