1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NXP SJA1105 Automotive Ethernet Switch Family 8 9description: 10 The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at 11 least one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum 12 cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed 13 depends on the SPI bus master driver. 14 15maintainers: 16 - Vladimir Oltean <vladimir.oltean@nxp.com> 17 18properties: 19 compatible: 20 enum: 21 - nxp,sja1105e 22 - nxp,sja1105t 23 - nxp,sja1105p 24 - nxp,sja1105q 25 - nxp,sja1105r 26 - nxp,sja1105s 27 - nxp,sja1110a 28 - nxp,sja1110b 29 - nxp,sja1110c 30 - nxp,sja1110d 31 32 reg: 33 maxItems: 1 34 35 spi-cpha: true 36 spi-cpol: true 37 38 # Optional container node for the 2 internal MDIO buses of the SJA1110 39 # (one for the internal 100base-T1 PHYs and the other for the single 40 # 100base-TX PHY). The "reg" property does not have physical significance. 41 # The PHY addresses to port correspondence is as follows: for 100base-T1, 42 # port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has 43 # PHY 1. 44 mdios: 45 type: object 46 47 properties: 48 '#address-cells': 49 const: 1 50 '#size-cells': 51 const: 0 52 53 patternProperties: 54 "^mdio@[0-1]$": 55 $ref: /schemas/net/mdio.yaml# 56 unevaluatedProperties: false 57 58 properties: 59 compatible: 60 oneOf: 61 - enum: 62 - nxp,sja1110-base-t1-mdio 63 - nxp,sja1110-base-tx-mdio 64 65 reg: 66 oneOf: 67 - enum: 68 - 0 69 - 1 70 71 required: 72 - compatible 73 - reg 74 75patternProperties: 76 "^(ethernet-)?ports$": 77 patternProperties: 78 "^(ethernet-)?port@[0-9]+$": 79 allOf: 80 - if: 81 properties: 82 phy-mode: 83 contains: 84 enum: 85 - rgmii 86 - rgmii-rxid 87 - rgmii-txid 88 - rgmii-id 89 then: 90 properties: 91 rx-internal-delay-ps: 92 $ref: "#/$defs/internal-delay-ps" 93 tx-internal-delay-ps: 94 $ref: "#/$defs/internal-delay-ps" 95 96required: 97 - compatible 98 - reg 99 100$defs: 101 internal-delay-ps: 102 description: 103 Disable tunable delay lines using 0 ps, or enable them and select 104 the phase between 1640 ps (73.8 degree shift at 1Gbps) and 2260 ps 105 (101.7 degree shift) in increments of 0.9 degrees (20 ps). 106 enum: 107 [0, 1640, 1660, 1680, 1700, 1720, 1740, 1760, 1780, 1800, 1820, 1840, 108 1860, 1880, 1900, 1920, 1940, 1960, 1980, 2000, 2020, 2040, 2060, 2080, 109 2100, 2120, 2140, 2160, 2180, 2200, 2220, 2240, 2260] 110 111allOf: 112 - $ref: dsa.yaml#/$defs/ethernet-ports 113 - $ref: /schemas/spi/spi-peripheral-props.yaml# 114 - if: 115 properties: 116 compatible: 117 enum: 118 - nxp,sja1105e 119 - nxp,sja1105p 120 - nxp,sja1105q 121 - nxp,sja1105r 122 - nxp,sja1105s 123 - nxp,sja1105t 124 then: 125 properties: 126 spi-cpol: false 127 required: 128 - spi-cpha 129 else: 130 properties: 131 spi-cpha: false 132 required: 133 - spi-cpol 134 135unevaluatedProperties: false 136 137examples: 138 - | 139 spi { 140 #address-cells = <1>; 141 #size-cells = <0>; 142 143 ethernet-switch@1 { 144 reg = <0x1>; 145 compatible = "nxp,sja1105t"; 146 spi-cpha; 147 148 ethernet-ports { 149 #address-cells = <1>; 150 #size-cells = <0>; 151 152 port@0 { 153 phy-handle = <&rgmii_phy6>; 154 phy-mode = "rgmii-id"; 155 rx-internal-delay-ps = <0>; 156 tx-internal-delay-ps = <0>; 157 reg = <0>; 158 }; 159 160 port@1 { 161 phy-handle = <&rgmii_phy3>; 162 phy-mode = "rgmii-id"; 163 rx-internal-delay-ps = <0>; 164 tx-internal-delay-ps = <0>; 165 reg = <1>; 166 }; 167 168 port@2 { 169 phy-handle = <&rgmii_phy4>; 170 phy-mode = "rgmii-id"; 171 rx-internal-delay-ps = <0>; 172 tx-internal-delay-ps = <0>; 173 reg = <2>; 174 }; 175 176 port@3 { 177 phy-handle = <&rgmii_phy4>; 178 phy-mode = "rgmii-id"; 179 rx-internal-delay-ps = <0>; 180 tx-internal-delay-ps = <0>; 181 reg = <3>; 182 }; 183 184 port@4 { 185 ethernet = <&enet2>; 186 phy-mode = "rgmii"; 187 rx-internal-delay-ps = <0>; 188 tx-internal-delay-ps = <0>; 189 reg = <4>; 190 191 fixed-link { 192 speed = <1000>; 193 full-duplex; 194 }; 195 }; 196 }; 197 }; 198 }; 199