xref: /freebsd/sys/contrib/device-tree/Bindings/net/dsa/nxp,sja1105.yaml (revision 8cc087a1eee9ec1ca9f7ac1e63ad51bdb5a682eb) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP SJA1105 Automotive Ethernet Switch Family Device Tree Bindings
8
9description:
10  The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
11  least one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum
12  cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed
13  depends on the SPI bus master driver.
14
15allOf:
16  - $ref: "dsa.yaml#"
17
18maintainers:
19  - Vladimir Oltean <vladimir.oltean@nxp.com>
20
21properties:
22  compatible:
23    enum:
24      - nxp,sja1105e
25      - nxp,sja1105t
26      - nxp,sja1105p
27      - nxp,sja1105q
28      - nxp,sja1105r
29      - nxp,sja1105s
30      - nxp,sja1110a
31      - nxp,sja1110b
32      - nxp,sja1110c
33      - nxp,sja1110d
34
35  reg:
36    maxItems: 1
37
38  # Optional container node for the 2 internal MDIO buses of the SJA1110
39  # (one for the internal 100base-T1 PHYs and the other for the single
40  # 100base-TX PHY). The "reg" property does not have physical significance.
41  # The PHY addresses to port correspondence is as follows: for 100base-T1,
42  # port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has
43  # PHY 1.
44  mdios:
45    type: object
46
47    properties:
48      '#address-cells':
49        const: 1
50      '#size-cells':
51        const: 0
52
53    patternProperties:
54      "^mdio@[0-1]$":
55        type: object
56
57        allOf:
58          - $ref: "http://devicetree.org/schemas/net/mdio.yaml#"
59
60        properties:
61          compatible:
62            oneOf:
63              - enum:
64                  - nxp,sja1110-base-t1-mdio
65                  - nxp,sja1110-base-tx-mdio
66
67          reg:
68            oneOf:
69              - enum:
70                  - 0
71                  - 1
72
73        required:
74          - compatible
75          - reg
76
77patternProperties:
78  "^(ethernet-)?ports$":
79    patternProperties:
80      "^(ethernet-)?port@[0-9]+$":
81        allOf:
82          - if:
83              properties:
84                phy-mode:
85                  contains:
86                    enum:
87                      - rgmii
88                      - rgmii-rxid
89                      - rgmii-txid
90                      - rgmii-id
91            then:
92              properties:
93                rx-internal-delay-ps:
94                  $ref: "#/$defs/internal-delay-ps"
95                tx-internal-delay-ps:
96                  $ref: "#/$defs/internal-delay-ps"
97
98required:
99  - compatible
100  - reg
101
102$defs:
103  internal-delay-ps:
104    description:
105      Disable tunable delay lines using 0 ps, or enable them and select
106      the phase between 1640 ps (73.8 degree shift at 1Gbps) and 2260 ps
107      (101.7 degree shift) in increments of 0.9 degrees (20 ps).
108    enum:
109      [0, 1640, 1660, 1680, 1700, 1720, 1740, 1760, 1780, 1800, 1820, 1840,
110       1860, 1880, 1900, 1920, 1940, 1960, 1980, 2000, 2020, 2040, 2060, 2080,
111       2100, 2120, 2140, 2160, 2180, 2200, 2220, 2240, 2260]
112
113unevaluatedProperties: false
114
115examples:
116  - |
117    spi {
118            #address-cells = <1>;
119            #size-cells = <0>;
120
121            ethernet-switch@1 {
122                    reg = <0x1>;
123                    compatible = "nxp,sja1105t";
124
125                    ethernet-ports {
126                            #address-cells = <1>;
127                            #size-cells = <0>;
128
129                            port@0 {
130                                    phy-handle = <&rgmii_phy6>;
131                                    phy-mode = "rgmii-id";
132                                    rx-internal-delay-ps = <0>;
133                                    tx-internal-delay-ps = <0>;
134                                    reg = <0>;
135                            };
136
137                            port@1 {
138                                    phy-handle = <&rgmii_phy3>;
139                                    phy-mode = "rgmii-id";
140                                    rx-internal-delay-ps = <0>;
141                                    tx-internal-delay-ps = <0>;
142                                    reg = <1>;
143                            };
144
145                            port@2 {
146                                    phy-handle = <&rgmii_phy4>;
147                                    phy-mode = "rgmii-id";
148                                    rx-internal-delay-ps = <0>;
149                                    tx-internal-delay-ps = <0>;
150                                    reg = <2>;
151                            };
152
153                            port@3 {
154                                    phy-handle = <&rgmii_phy4>;
155                                    phy-mode = "rgmii-id";
156                                    rx-internal-delay-ps = <0>;
157                                    tx-internal-delay-ps = <0>;
158                                    reg = <3>;
159                            };
160
161                            port@4 {
162                                    ethernet = <&enet2>;
163                                    phy-mode = "rgmii";
164                                    rx-internal-delay-ps = <0>;
165                                    tx-internal-delay-ps = <0>;
166                                    reg = <4>;
167
168                                    fixed-link {
169                                            speed = <1000>;
170                                            full-duplex;
171                                    };
172                            };
173                    };
174            };
175    };
176