1Mediatek MT7530 Ethernet switch 2================================ 3 4Required properties: 5 6- compatible: may be compatible = "mediatek,mt7530" 7 or compatible = "mediatek,mt7621" 8 or compatible = "mediatek,mt7531" 9- #address-cells: Must be 1. 10- #size-cells: Must be 0. 11- mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part 12 on multi-chip module belong to MT7623A has or the remotely standalone 13 chip as the function MT7623N reference board provided for. 14 15If compatible mediatek,mt7530 is set then the following properties are required 16 17- core-supply: Phandle to the regulator node necessary for the core power. 18- io-supply: Phandle to the regulator node necessary for the I/O power. 19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt 20 for details for the regulator setup on these boards. 21 22If the property mediatek,mcm isn't defined, following property is required 23 24- reset-gpios: Should be a gpio specifier for a reset line. 25 26Else, following properties are required 27 28- resets : Phandle pointing to the system reset controller with 29 line index for the ethsys. 30- reset-names : Should be set to "mcm". 31 32Required properties for the child nodes within ports container: 33 34- reg: Port address described must be 6 for CPU port and from 0 to 5 for 35 user ports. 36- phy-mode: String, the following values are acceptable for port labeled 37 "cpu": 38 If compatible mediatek,mt7530 or mediatek,mt7621 is set, 39 must be either "trgmii" or "rgmii" 40 If compatible mediatek,mt7531 is set, 41 must be either "sgmii", "1000base-x" or "2500base-x" 42 43Port 5 of mt7530 and mt7621 switch is muxed between: 441. GMAC5: GMAC5 can interface with another external MAC or PHY. 452. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC 46 of the SOC. Used in many setups where port 0/4 becomes the WAN port. 47 Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to 48 GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not 49 connected to external component! 50 51Port 5 modes/configurations: 521. Port 5 is disabled and isolated: An external phy can interface to the 2nd 53 GMAC of the SOC. 54 In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd 55 GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC! 562. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC. 57 It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode 58 and RGMII delay. 593. Port 5 is muxed to GMAC5 and can interface to an external phy. 60 Port 5 becomes an extra switch port. 61 Only works on platform where external phy TX<->RX lines are swapped. 62 Like in the Ubiquiti ER-X-SFP. 634. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port. 64 Currently a 2nd CPU port is not supported by DSA code. 65 66Depending on how the external PHY is wired: 671. normal: The PHY can only connect to 2nd GMAC but not to the switch 682. swapped: RGMII TX, RX are swapped; external phy interface with the switch as 69 a ethernet port. But can't interface to the 2nd GMAC. 70 71Based on the DT the port 5 mode is configured. 72 73Driver tries to lookup the phy-handle of the 2nd GMAC of the master device. 74When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2. 75phy-mode must be set, see also example 2 below! 76 * mt7621: phy-mode = "rgmii-txid"; 77 * mt7623: phy-mode = "rgmii"; 78 79Optional properties: 80 81- gpio-controller: Boolean; if defined, MT7530's LED controller will run on 82 GPIO mode. 83- #gpio-cells: Must be 2 if gpio-controller is defined. 84- interrupt-controller: Boolean; Enables the internal interrupt controller. 85 86If interrupt-controller is defined, the following properties are required. 87 88- #interrupt-cells: Must be 1. 89- interrupts: Parent interrupt for the interrupt controller. 90 91See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional 92required, optional properties and how the integrated switch subnodes must 93be specified. 94 95Example: 96 97 &mdio0 { 98 switch@0 { 99 compatible = "mediatek,mt7530"; 100 #address-cells = <1>; 101 #size-cells = <0>; 102 reg = <0>; 103 104 core-supply = <&mt6323_vpa_reg>; 105 io-supply = <&mt6323_vemc3v3_reg>; 106 reset-gpios = <&pio 33 0>; 107 108 ports { 109 #address-cells = <1>; 110 #size-cells = <0>; 111 reg = <0>; 112 port@0 { 113 reg = <0>; 114 label = "lan0"; 115 }; 116 117 port@1 { 118 reg = <1>; 119 label = "lan1"; 120 }; 121 122 port@2 { 123 reg = <2>; 124 label = "lan2"; 125 }; 126 127 port@3 { 128 reg = <3>; 129 label = "lan3"; 130 }; 131 132 port@4 { 133 reg = <4>; 134 label = "wan"; 135 }; 136 137 port@6 { 138 reg = <6>; 139 label = "cpu"; 140 ethernet = <&gmac0>; 141 phy-mode = "trgmii"; 142 fixed-link { 143 speed = <1000>; 144 full-duplex; 145 }; 146 }; 147 }; 148 }; 149 }; 150 151Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4. 152 153ð { 154 gmac0: mac@0 { 155 compatible = "mediatek,eth-mac"; 156 reg = <0>; 157 phy-mode = "rgmii"; 158 159 fixed-link { 160 speed = <1000>; 161 full-duplex; 162 pause; 163 }; 164 }; 165 166 gmac1: mac@1 { 167 compatible = "mediatek,eth-mac"; 168 reg = <1>; 169 phy-mode = "rgmii-txid"; 170 phy-handle = <&phy4>; 171 }; 172 173 mdio: mdio-bus { 174 #address-cells = <1>; 175 #size-cells = <0>; 176 177 /* Internal phy */ 178 phy4: ethernet-phy@4 { 179 reg = <4>; 180 }; 181 182 mt7530: switch@1f { 183 compatible = "mediatek,mt7621"; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 reg = <0x1f>; 187 pinctrl-names = "default"; 188 mediatek,mcm; 189 190 resets = <&rstctrl 2>; 191 reset-names = "mcm"; 192 193 ports { 194 #address-cells = <1>; 195 #size-cells = <0>; 196 197 port@0 { 198 reg = <0>; 199 label = "lan0"; 200 }; 201 202 port@1 { 203 reg = <1>; 204 label = "lan1"; 205 }; 206 207 port@2 { 208 reg = <2>; 209 label = "lan2"; 210 }; 211 212 port@3 { 213 reg = <3>; 214 label = "lan3"; 215 }; 216 217/* Commented out. Port 4 is handled by 2nd GMAC. 218 port@4 { 219 reg = <4>; 220 label = "lan4"; 221 }; 222*/ 223 224 cpu_port0: port@6 { 225 reg = <6>; 226 label = "cpu"; 227 ethernet = <&gmac0>; 228 phy-mode = "rgmii"; 229 230 fixed-link { 231 speed = <1000>; 232 full-duplex; 233 pause; 234 }; 235 }; 236 }; 237 }; 238 }; 239}; 240 241Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY. 242 243ð { 244 gmac0: mac@0 { 245 compatible = "mediatek,eth-mac"; 246 reg = <0>; 247 phy-mode = "rgmii"; 248 249 fixed-link { 250 speed = <1000>; 251 full-duplex; 252 pause; 253 }; 254 }; 255 256 mdio: mdio-bus { 257 #address-cells = <1>; 258 #size-cells = <0>; 259 260 /* External phy */ 261 ephy5: ethernet-phy@7 { 262 reg = <7>; 263 }; 264 265 mt7530: switch@1f { 266 compatible = "mediatek,mt7621"; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 reg = <0x1f>; 270 pinctrl-names = "default"; 271 mediatek,mcm; 272 273 resets = <&rstctrl 2>; 274 reset-names = "mcm"; 275 276 ports { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 280 port@0 { 281 reg = <0>; 282 label = "lan0"; 283 }; 284 285 port@1 { 286 reg = <1>; 287 label = "lan1"; 288 }; 289 290 port@2 { 291 reg = <2>; 292 label = "lan2"; 293 }; 294 295 port@3 { 296 reg = <3>; 297 label = "lan3"; 298 }; 299 300 port@4 { 301 reg = <4>; 302 label = "lan4"; 303 }; 304 305 port@5 { 306 reg = <5>; 307 label = "lan5"; 308 phy-mode = "rgmii"; 309 phy-handle = <&ephy5>; 310 }; 311 312 cpu_port0: port@6 { 313 reg = <6>; 314 label = "cpu"; 315 ethernet = <&gmac0>; 316 phy-mode = "rgmii"; 317 318 fixed-link { 319 speed = <1000>; 320 full-duplex; 321 pause; 322 }; 323 }; 324 }; 325 }; 326 }; 327}; 328