1Mediatek MT7530 Ethernet switch 2================================ 3 4Required properties: 5 6- compatible: may be compatible = "mediatek,mt7530" 7 or compatible = "mediatek,mt7621" 8 or compatible = "mediatek,mt7531" 9- #address-cells: Must be 1. 10- #size-cells: Must be 0. 11- mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part 12 on multi-chip module belong to MT7623A has or the remotely standalone 13 chip as the function MT7623N reference board provided for. 14 15If compatible mediatek,mt7530 is set then the following properties are required 16 17- core-supply: Phandle to the regulator node necessary for the core power. 18- io-supply: Phandle to the regulator node necessary for the I/O power. 19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt 20 for details for the regulator setup on these boards. 21 22If the property mediatek,mcm isn't defined, following property is required 23 24- reset-gpios: Should be a gpio specifier for a reset line. 25 26Else, following properties are required 27 28- resets : Phandle pointing to the system reset controller with 29 line index for the ethsys. 30- reset-names : Should be set to "mcm". 31 32Required properties for the child nodes within ports container: 33 34- reg: Port address described must be 6 for CPU port and from 0 to 5 for 35 user ports. 36- phy-mode: String, the following values are acceptable for port labeled 37 "cpu": 38 If compatible mediatek,mt7530 or mediatek,mt7621 is set, 39 must be either "trgmii" or "rgmii" 40 If compatible mediatek,mt7531 is set, 41 must be either "sgmii", "1000base-x" or "2500base-x" 42 43Port 5 of mt7530 and mt7621 switch is muxed between: 441. GMAC5: GMAC5 can interface with another external MAC or PHY. 452. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC 46 of the SOC. Used in many setups where port 0/4 becomes the WAN port. 47 Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to 48 GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not 49 connected to external component! 50 51Port 5 modes/configurations: 521. Port 5 is disabled and isolated: An external phy can interface to the 2nd 53 GMAC of the SOC. 54 In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd 55 GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC! 562. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC. 57 It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode 58 and RGMII delay. 593. Port 5 is muxed to GMAC5 and can interface to an external phy. 60 Port 5 becomes an extra switch port. 61 Only works on platform where external phy TX<->RX lines are swapped. 62 Like in the Ubiquiti ER-X-SFP. 634. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port. 64 Currently a 2nd CPU port is not supported by DSA code. 65 66Depending on how the external PHY is wired: 671. normal: The PHY can only connect to 2nd GMAC but not to the switch 682. swapped: RGMII TX, RX are swapped; external phy interface with the switch as 69 a ethernet port. But can't interface to the 2nd GMAC. 70 71Based on the DT the port 5 mode is configured. 72 73Driver tries to lookup the phy-handle of the 2nd GMAC of the master device. 74When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2. 75phy-mode must be set, see also example 2 below! 76 * mt7621: phy-mode = "rgmii-txid"; 77 * mt7623: phy-mode = "rgmii"; 78 79See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional 80required, optional properties and how the integrated switch subnodes must 81be specified. 82 83Example: 84 85 &mdio0 { 86 switch@0 { 87 compatible = "mediatek,mt7530"; 88 #address-cells = <1>; 89 #size-cells = <0>; 90 reg = <0>; 91 92 core-supply = <&mt6323_vpa_reg>; 93 io-supply = <&mt6323_vemc3v3_reg>; 94 reset-gpios = <&pio 33 0>; 95 96 ports { 97 #address-cells = <1>; 98 #size-cells = <0>; 99 reg = <0>; 100 port@0 { 101 reg = <0>; 102 label = "lan0"; 103 }; 104 105 port@1 { 106 reg = <1>; 107 label = "lan1"; 108 }; 109 110 port@2 { 111 reg = <2>; 112 label = "lan2"; 113 }; 114 115 port@3 { 116 reg = <3>; 117 label = "lan3"; 118 }; 119 120 port@4 { 121 reg = <4>; 122 label = "wan"; 123 }; 124 125 port@6 { 126 reg = <6>; 127 label = "cpu"; 128 ethernet = <&gmac0>; 129 phy-mode = "trgmii"; 130 fixed-link { 131 speed = <1000>; 132 full-duplex; 133 }; 134 }; 135 }; 136 }; 137 }; 138 139Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4. 140 141ð { 142 gmac0: mac@0 { 143 compatible = "mediatek,eth-mac"; 144 reg = <0>; 145 phy-mode = "rgmii"; 146 147 fixed-link { 148 speed = <1000>; 149 full-duplex; 150 pause; 151 }; 152 }; 153 154 gmac1: mac@1 { 155 compatible = "mediatek,eth-mac"; 156 reg = <1>; 157 phy-mode = "rgmii-txid"; 158 phy-handle = <&phy4>; 159 }; 160 161 mdio: mdio-bus { 162 #address-cells = <1>; 163 #size-cells = <0>; 164 165 /* Internal phy */ 166 phy4: ethernet-phy@4 { 167 reg = <4>; 168 }; 169 170 mt7530: switch@1f { 171 compatible = "mediatek,mt7621"; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 reg = <0x1f>; 175 pinctrl-names = "default"; 176 mediatek,mcm; 177 178 resets = <&rstctrl 2>; 179 reset-names = "mcm"; 180 181 ports { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 185 port@0 { 186 reg = <0>; 187 label = "lan0"; 188 }; 189 190 port@1 { 191 reg = <1>; 192 label = "lan1"; 193 }; 194 195 port@2 { 196 reg = <2>; 197 label = "lan2"; 198 }; 199 200 port@3 { 201 reg = <3>; 202 label = "lan3"; 203 }; 204 205/* Commented out. Port 4 is handled by 2nd GMAC. 206 port@4 { 207 reg = <4>; 208 label = "lan4"; 209 }; 210*/ 211 212 cpu_port0: port@6 { 213 reg = <6>; 214 label = "cpu"; 215 ethernet = <&gmac0>; 216 phy-mode = "rgmii"; 217 218 fixed-link { 219 speed = <1000>; 220 full-duplex; 221 pause; 222 }; 223 }; 224 }; 225 }; 226 }; 227}; 228 229Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY. 230 231ð { 232 gmac0: mac@0 { 233 compatible = "mediatek,eth-mac"; 234 reg = <0>; 235 phy-mode = "rgmii"; 236 237 fixed-link { 238 speed = <1000>; 239 full-duplex; 240 pause; 241 }; 242 }; 243 244 mdio: mdio-bus { 245 #address-cells = <1>; 246 #size-cells = <0>; 247 248 /* External phy */ 249 ephy5: ethernet-phy@7 { 250 reg = <7>; 251 }; 252 253 mt7530: switch@1f { 254 compatible = "mediatek,mt7621"; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 reg = <0x1f>; 258 pinctrl-names = "default"; 259 mediatek,mcm; 260 261 resets = <&rstctrl 2>; 262 reset-names = "mcm"; 263 264 ports { 265 #address-cells = <1>; 266 #size-cells = <0>; 267 268 port@0 { 269 reg = <0>; 270 label = "lan0"; 271 }; 272 273 port@1 { 274 reg = <1>; 275 label = "lan1"; 276 }; 277 278 port@2 { 279 reg = <2>; 280 label = "lan2"; 281 }; 282 283 port@3 { 284 reg = <3>; 285 label = "lan3"; 286 }; 287 288 port@4 { 289 reg = <4>; 290 label = "lan4"; 291 }; 292 293 port@5 { 294 reg = <5>; 295 label = "lan5"; 296 phy-mode = "rgmii"; 297 phy-handle = <&ephy5>; 298 }; 299 300 cpu_port0: port@6 { 301 reg = <6>; 302 label = "cpu"; 303 ethernet = <&gmac0>; 304 phy-mode = "rgmii"; 305 306 fixed-link { 307 speed = <1000>; 308 full-duplex; 309 pause; 310 }; 311 }; 312 }; 313 }; 314 }; 315}; 316