1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Microchip KSZ Series Ethernet switches 8 9maintainers: 10 - Marek Vasut <marex@denx.de> 11 - Woojung Huh <Woojung.Huh@microchip.com> 12 13allOf: 14 - $ref: dsa.yaml#/$defs/ethernet-ports 15 - $ref: /schemas/spi/spi-peripheral-props.yaml# 16 17properties: 18 # See Documentation/devicetree/bindings/net/dsa/dsa.yaml for a list of additional 19 # required and optional properties. 20 compatible: 21 enum: 22 - microchip,ksz8765 23 - microchip,ksz8794 24 - microchip,ksz8795 25 - microchip,ksz8863 26 - microchip,ksz8873 27 - microchip,ksz9477 28 - microchip,ksz9897 29 - microchip,ksz9896 30 - microchip,ksz9567 31 - microchip,ksz8565 32 - microchip,ksz9893 33 - microchip,ksz9563 34 - microchip,ksz8563 35 36 reset-gpios: 37 description: 38 Should be a gpio specifier for a reset line. 39 maxItems: 1 40 41 wakeup-source: true 42 43 microchip,synclko-125: 44 $ref: /schemas/types.yaml#/definitions/flag 45 description: 46 Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz. 47 48 microchip,synclko-disable: 49 $ref: /schemas/types.yaml#/definitions/flag 50 description: 51 Set if the output SYNCLKO clock should be disabled. Do not mix with 52 microchip,synclko-125. 53 54 microchip,io-drive-strength-microamp: 55 description: 56 IO Pad Drive Strength 57 enum: [8000, 16000] 58 default: 16000 59 60 microchip,hi-drive-strength-microamp: 61 description: 62 High Speed Drive Strength. Controls drive strength of GMII / RGMII / 63 MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines. 64 enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000] 65 default: 24000 66 67 microchip,lo-drive-strength-microamp: 68 description: 69 Low Speed Drive Strength. Controls drive strength of TX_CLK / REFCLKI, 70 COL, CRS, LEDs, PME_N, NTRP_N, SDO and SDI/SDA/MDIO lines. 71 enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000] 72 default: 8000 73 74 interrupts: 75 maxItems: 1 76 77required: 78 - compatible 79 - reg 80 81unevaluatedProperties: false 82 83examples: 84 - | 85 #include <dt-bindings/gpio/gpio.h> 86 87 // Ethernet switch connected via SPI to the host, CPU port wired to eth0: 88 eth0 { 89 fixed-link { 90 speed = <1000>; 91 full-duplex; 92 }; 93 }; 94 95 spi { 96 #address-cells = <1>; 97 #size-cells = <0>; 98 99 pinctrl-0 = <&pinctrl_spi_ksz>; 100 cs-gpios = <&pioC 25 0>; 101 id = <1>; 102 103 ksz9477: switch@0 { 104 compatible = "microchip,ksz9477"; 105 reg = <0>; 106 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 107 108 spi-max-frequency = <44000000>; 109 110 ethernet-ports { 111 #address-cells = <1>; 112 #size-cells = <0>; 113 port@0 { 114 reg = <0>; 115 label = "lan1"; 116 }; 117 port@1 { 118 reg = <1>; 119 label = "lan2"; 120 }; 121 port@2 { 122 reg = <2>; 123 label = "lan3"; 124 }; 125 port@3 { 126 reg = <3>; 127 label = "lan4"; 128 }; 129 port@4 { 130 reg = <4>; 131 label = "lan5"; 132 }; 133 port@5 { 134 reg = <5>; 135 ethernet = <ð0>; 136 phy-mode = "rgmii"; 137 138 fixed-link { 139 speed = <1000>; 140 full-duplex; 141 }; 142 }; 143 }; 144 }; 145 146 ksz8565: switch@1 { 147 compatible = "microchip,ksz8565"; 148 reg = <1>; 149 150 spi-max-frequency = <44000000>; 151 152 ethernet-ports { 153 #address-cells = <1>; 154 #size-cells = <0>; 155 port@0 { 156 reg = <0>; 157 label = "lan1"; 158 }; 159 port@1 { 160 reg = <1>; 161 label = "lan2"; 162 }; 163 port@2 { 164 reg = <2>; 165 label = "lan3"; 166 }; 167 port@3 { 168 reg = <3>; 169 label = "lan4"; 170 }; 171 port@6 { 172 reg = <6>; 173 ethernet = <ð0>; 174 phy-mode = "rgmii"; 175 176 fixed-link { 177 speed = <1000>; 178 full-duplex; 179 }; 180 }; 181 }; 182 }; 183 }; 184... 185