1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek MT7530 Ethernet switch 8 9maintainers: 10 - Sean Wang <sean.wang@mediatek.com> 11 - Landen Chao <Landen.Chao@mediatek.com> 12 - DENG Qingfang <dqfext@gmail.com> 13 14description: | 15 Port 5 of mt7530 and mt7621 switch is muxed between: 16 1. GMAC5: GMAC5 can interface with another external MAC or PHY. 17 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC 18 of the SOC. Used in many setups where port 0/4 becomes the WAN port. 19 Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to 20 GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not 21 connected to external component! 22 23 Port 5 modes/configurations: 24 1. Port 5 is disabled and isolated: An external phy can interface to the 2nd 25 GMAC of the SOC. 26 In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd 27 GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC! 28 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC. 29 It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode 30 and RGMII delay. 31 3. Port 5 is muxed to GMAC5 and can interface to an external phy. 32 Port 5 becomes an extra switch port. 33 Only works on platform where external phy TX<->RX lines are swapped. 34 Like in the Ubiquiti ER-X-SFP. 35 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port. 36 Currently a 2nd CPU port is not supported by DSA code. 37 38 Depending on how the external PHY is wired: 39 1. normal: The PHY can only connect to 2nd GMAC but not to the switch 40 2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as 41 a ethernet port. But can't interface to the 2nd GMAC. 42 43 Based on the DT the port 5 mode is configured. 44 45 Driver tries to lookup the phy-handle of the 2nd GMAC of the master device. 46 When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2. 47 phy-mode must be set, see also example 2 below! 48 * mt7621: phy-mode = "rgmii-txid"; 49 * mt7623: phy-mode = "rgmii"; 50 51 CPU-Ports need a phy-mode property: 52 Allowed values on mt7530 and mt7621: 53 - "rgmii" 54 - "trgmii" 55 On mt7531: 56 - "1000base-x" 57 - "2500base-x" 58 - "rgmii" 59 - "sgmii" 60 61 62properties: 63 compatible: 64 enum: 65 - mediatek,mt7530 66 - mediatek,mt7531 67 - mediatek,mt7621 68 69 reg: 70 maxItems: 1 71 72 core-supply: 73 description: 74 Phandle to the regulator node necessary for the core power. 75 76 "#gpio-cells": 77 const: 2 78 79 gpio-controller: 80 type: boolean 81 description: 82 if defined, MT7530's LED controller will run on GPIO mode. 83 84 "#interrupt-cells": 85 const: 1 86 87 interrupt-controller: true 88 89 interrupts: 90 maxItems: 1 91 92 io-supply: 93 description: 94 Phandle to the regulator node necessary for the I/O power. 95 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt 96 for details for the regulator setup on these boards. 97 98 mediatek,mcm: 99 type: boolean 100 description: 101 if defined, indicates that either MT7530 is the part on multi-chip 102 module belong to MT7623A has or the remotely standalone chip as the 103 function MT7623N reference board provided for. 104 105 reset-gpios: 106 maxItems: 1 107 108 reset-names: 109 const: mcm 110 111 resets: 112 description: 113 Phandle pointing to the system reset controller with line index for 114 the ethsys. 115 maxItems: 1 116 117patternProperties: 118 "^(ethernet-)?ports$": 119 type: object 120 121 patternProperties: 122 "^(ethernet-)?port@[0-9]+$": 123 type: object 124 description: Ethernet switch ports 125 126 unevaluatedProperties: false 127 128 properties: 129 reg: 130 description: 131 Port address described must be 5 or 6 for CPU port and from 0 132 to 5 for user ports. 133 134 allOf: 135 - $ref: dsa-port.yaml# 136 - if: 137 properties: 138 label: 139 items: 140 - const: cpu 141 then: 142 required: 143 - reg 144 - phy-mode 145 146required: 147 - compatible 148 - reg 149 150allOf: 151 - $ref: "dsa.yaml#" 152 - if: 153 required: 154 - mediatek,mcm 155 then: 156 required: 157 - resets 158 - reset-names 159 160 - dependencies: 161 interrupt-controller: [ interrupts ] 162 163 - if: 164 properties: 165 compatible: 166 items: 167 - const: mediatek,mt7530 168 then: 169 required: 170 - core-supply 171 - io-supply 172 173unevaluatedProperties: false 174 175examples: 176 - | 177 #include <dt-bindings/gpio/gpio.h> 178 mdio { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 switch@0 { 182 compatible = "mediatek,mt7530"; 183 reg = <0>; 184 185 core-supply = <&mt6323_vpa_reg>; 186 io-supply = <&mt6323_vemc3v3_reg>; 187 reset-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; 188 189 ethernet-ports { 190 #address-cells = <1>; 191 #size-cells = <0>; 192 port@0 { 193 reg = <0>; 194 label = "lan0"; 195 }; 196 197 port@1 { 198 reg = <1>; 199 label = "lan1"; 200 }; 201 202 port@2 { 203 reg = <2>; 204 label = "lan2"; 205 }; 206 207 port@3 { 208 reg = <3>; 209 label = "lan3"; 210 }; 211 212 port@4 { 213 reg = <4>; 214 label = "wan"; 215 }; 216 217 port@6 { 218 reg = <6>; 219 label = "cpu"; 220 ethernet = <&gmac0>; 221 phy-mode = "trgmii"; 222 fixed-link { 223 speed = <1000>; 224 full-duplex; 225 }; 226 }; 227 }; 228 }; 229 }; 230 231 - | 232 //Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4. 233 234 ethernet { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 gmac0: mac@0 { 238 compatible = "mediatek,eth-mac"; 239 reg = <0>; 240 phy-mode = "rgmii"; 241 242 fixed-link { 243 speed = <1000>; 244 full-duplex; 245 pause; 246 }; 247 }; 248 249 gmac1: mac@1 { 250 compatible = "mediatek,eth-mac"; 251 reg = <1>; 252 phy-mode = "rgmii-txid"; 253 phy-handle = <&phy4>; 254 }; 255 256 mdio: mdio-bus { 257 #address-cells = <1>; 258 #size-cells = <0>; 259 260 /* Internal phy */ 261 phy4: ethernet-phy@4 { 262 reg = <4>; 263 }; 264 265 mt7530: switch@1f { 266 compatible = "mediatek,mt7621"; 267 reg = <0x1f>; 268 mediatek,mcm; 269 270 resets = <&rstctrl 2>; 271 reset-names = "mcm"; 272 273 ethernet-ports { 274 #address-cells = <1>; 275 #size-cells = <0>; 276 277 port@0 { 278 reg = <0>; 279 label = "lan0"; 280 }; 281 282 port@1 { 283 reg = <1>; 284 label = "lan1"; 285 }; 286 287 port@2 { 288 reg = <2>; 289 label = "lan2"; 290 }; 291 292 port@3 { 293 reg = <3>; 294 label = "lan3"; 295 }; 296 297 /* Commented out. Port 4 is handled by 2nd GMAC. 298 port@4 { 299 reg = <4>; 300 label = "lan4"; 301 }; 302 */ 303 304 port@6 { 305 reg = <6>; 306 label = "cpu"; 307 ethernet = <&gmac0>; 308 phy-mode = "rgmii"; 309 310 fixed-link { 311 speed = <1000>; 312 full-duplex; 313 pause; 314 }; 315 }; 316 }; 317 }; 318 }; 319 }; 320 321 - | 322 //Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY. 323 324 ethernet { 325 #address-cells = <1>; 326 #size-cells = <0>; 327 gmac_0: mac@0 { 328 compatible = "mediatek,eth-mac"; 329 reg = <0>; 330 phy-mode = "rgmii"; 331 332 fixed-link { 333 speed = <1000>; 334 full-duplex; 335 pause; 336 }; 337 }; 338 339 mdio0: mdio-bus { 340 #address-cells = <1>; 341 #size-cells = <0>; 342 343 /* External phy */ 344 ephy5: ethernet-phy@7 { 345 reg = <7>; 346 }; 347 348 switch@1f { 349 compatible = "mediatek,mt7621"; 350 reg = <0x1f>; 351 mediatek,mcm; 352 353 resets = <&rstctrl 2>; 354 reset-names = "mcm"; 355 356 ethernet-ports { 357 #address-cells = <1>; 358 #size-cells = <0>; 359 360 port@0 { 361 reg = <0>; 362 label = "lan0"; 363 }; 364 365 port@1 { 366 reg = <1>; 367 label = "lan1"; 368 }; 369 370 port@2 { 371 reg = <2>; 372 label = "lan2"; 373 }; 374 375 port@3 { 376 reg = <3>; 377 label = "lan3"; 378 }; 379 380 port@4 { 381 reg = <4>; 382 label = "lan4"; 383 }; 384 385 port@5 { 386 reg = <5>; 387 label = "lan5"; 388 phy-mode = "rgmii"; 389 phy-handle = <&ephy5>; 390 }; 391 392 cpu_port0: port@6 { 393 reg = <6>; 394 label = "cpu"; 395 ethernet = <&gmac_0>; 396 phy-mode = "rgmii"; 397 398 fixed-link { 399 speed = <1000>; 400 full-duplex; 401 pause; 402 }; 403 }; 404 }; 405 }; 406 }; 407 }; 408