1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Mediatek MT7530 and MT7531 Ethernet Switches 8 9maintainers: 10 - Arınç ÜNAL <arinc.unal@arinc9.com> 11 - Landen Chao <Landen.Chao@mediatek.com> 12 - DENG Qingfang <dqfext@gmail.com> 13 - Sean Wang <sean.wang@mediatek.com> 14 - Daniel Golle <daniel@makrotopia.org> 15 16description: | 17 There are three versions of MT7530, standalone, in a multi-chip module and 18 built-into a SoC. 19 20 MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN, 21 MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. 22 23 The MT7988 SoC comes with a built-in switch similar to MT7531 as well as four 24 Gigabit Ethernet PHYs. The switch registers are directly mapped into the SoC's 25 memory map rather than using MDIO. The switch got an internally connected 10G 26 CPU port and 4 user ports connected to the built-in Gigabit Ethernet PHYs. 27 28 MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100 PHYs 29 and the switch registers are directly mapped into SoC's memory map rather than 30 using MDIO. The DSA driver currently doesn't support MT7620 variants. 31 32 There is only the standalone version of MT7531. 33 34 Port 5 on MT7530 has got various ways of configuration: 35 36 - Port 5 can be used as a CPU port. 37 38 - PHY 0 or 4 of the switch can be muxed to gmac5 of the switch. Therefore, 39 the gmac of the SoC which is wired to port 5 can connect to the PHY. 40 This is usually used for connecting the wan port directly to the CPU to 41 achieve 2 Gbps routing in total. 42 43 The driver looks up the reg on the ethernet-phy node, which the phy-handle 44 property on the gmac node refers to, to mux the specified phy. 45 46 The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the 47 compatible string and the reg must be 1. So, for now, only gmac1 of a 48 MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. 49 50 For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 51 52 Check out example 5. 53 54 - For the multi-chip module MT7530, in case of an external phy wired to 55 gmac1 of the SoC, port 5 must not be enabled. 56 57 In case of muxing PHY 0 or 4, the external phy must not be enabled. 58 59 For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. 60 61 Check out example 6. 62 63 - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave. 64 65 For the multi-chip module MT7530, the external phy must be wired TX to TX 66 to gmac1 of the SoC for this to work. Ubiquiti EdgeRouter X SFP is wired 67 this way. 68 69 For the multi-chip module MT7530, muxing PHY 0 or 4 won't work when the 70 external phy is connected TX to TX. 71 72 For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. 73 74 Check out example 7. 75 76properties: 77 compatible: 78 oneOf: 79 - description: 80 Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC 81 const: mediatek,mt7530 82 83 - description: 84 Standalone MT7531 85 const: mediatek,mt7531 86 87 - description: 88 Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 89 const: mediatek,mt7621 90 91 - description: 92 Built-in switch of the MT7988 SoC 93 const: mediatek,mt7988-switch 94 95 reg: 96 maxItems: 1 97 98 core-supply: 99 description: 100 Phandle to the regulator node necessary for the core power. 101 102 "#gpio-cells": 103 const: 2 104 105 gpio-controller: 106 type: boolean 107 description: | 108 If defined, LED controller of the MT7530 switch will run on GPIO mode. 109 110 There are 15 controllable pins. 111 port 0 LED 0..2 as GPIO 0..2 112 port 1 LED 0..2 as GPIO 3..5 113 port 2 LED 0..2 as GPIO 6..8 114 port 3 LED 0..2 as GPIO 9..11 115 port 4 LED 0..2 as GPIO 12..14 116 117 "#interrupt-cells": 118 const: 1 119 120 interrupt-controller: true 121 122 interrupts: 123 maxItems: 1 124 125 io-supply: 126 description: | 127 Phandle to the regulator node necessary for the I/O power. 128 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for 129 details for the regulator setup on these boards. 130 131 mediatek,mcm: 132 type: boolean 133 description: 134 Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530 135 switch is a part of the multi-chip module. 136 137 reset-gpios: 138 description: | 139 GPIO to reset the switch. Use this if mediatek,mcm is not used. 140 This property is optional because some boards share the reset line with 141 other components which makes it impossible to probe the switch if the 142 reset line is used. 143 maxItems: 1 144 145 reset-names: 146 const: mcm 147 148 resets: 149 description: 150 Phandle pointing to the system reset controller with line index for the 151 ethsys. 152 maxItems: 1 153 154patternProperties: 155 "^(ethernet-)?ports$": 156 type: object 157 158 patternProperties: 159 "^(ethernet-)?port@[0-9]+$": 160 type: object 161 162 properties: 163 reg: 164 description: 165 Port address described must be 5 or 6 for CPU port and from 0 to 5 166 for user ports. 167 168 allOf: 169 - if: 170 required: [ ethernet ] 171 then: 172 properties: 173 reg: 174 enum: 175 - 5 176 - 6 177 178required: 179 - compatible 180 - reg 181 182$defs: 183 mt7530-dsa-port: 184 patternProperties: 185 "^(ethernet-)?ports$": 186 patternProperties: 187 "^(ethernet-)?port@[0-9]+$": 188 if: 189 required: [ ethernet ] 190 then: 191 if: 192 properties: 193 reg: 194 const: 5 195 then: 196 properties: 197 phy-mode: 198 enum: 199 - gmii 200 - mii 201 - rgmii 202 else: 203 properties: 204 phy-mode: 205 enum: 206 - rgmii 207 - trgmii 208 209 mt7531-dsa-port: 210 patternProperties: 211 "^(ethernet-)?ports$": 212 patternProperties: 213 "^(ethernet-)?port@[0-9]+$": 214 if: 215 required: [ ethernet ] 216 then: 217 if: 218 properties: 219 reg: 220 const: 5 221 then: 222 properties: 223 phy-mode: 224 enum: 225 - 1000base-x 226 - 2500base-x 227 - rgmii 228 - sgmii 229 else: 230 properties: 231 phy-mode: 232 enum: 233 - 1000base-x 234 - 2500base-x 235 - sgmii 236 237allOf: 238 - $ref: dsa.yaml#/$defs/ethernet-ports 239 - if: 240 required: 241 - mediatek,mcm 242 then: 243 properties: 244 reset-gpios: false 245 246 required: 247 - resets 248 - reset-names 249 250 - dependencies: 251 interrupt-controller: [ interrupts ] 252 253 - if: 254 properties: 255 compatible: 256 const: mediatek,mt7530 257 then: 258 $ref: "#/$defs/mt7530-dsa-port" 259 required: 260 - core-supply 261 - io-supply 262 263 - if: 264 properties: 265 compatible: 266 const: mediatek,mt7531 267 then: 268 $ref: "#/$defs/mt7531-dsa-port" 269 properties: 270 gpio-controller: false 271 mediatek,mcm: false 272 273 - if: 274 properties: 275 compatible: 276 const: mediatek,mt7621 277 then: 278 $ref: "#/$defs/mt7530-dsa-port" 279 required: 280 - mediatek,mcm 281 282 - if: 283 properties: 284 compatible: 285 const: mediatek,mt7988-switch 286 then: 287 $ref: "#/$defs/mt7530-dsa-port" 288 properties: 289 gpio-controller: false 290 mediatek,mcm: false 291 reset-names: false 292 293unevaluatedProperties: false 294 295examples: 296 # Example 1: Standalone MT7530 297 - | 298 #include <dt-bindings/gpio/gpio.h> 299 300 mdio { 301 #address-cells = <1>; 302 #size-cells = <0>; 303 304 switch@1f { 305 compatible = "mediatek,mt7530"; 306 reg = <0x1f>; 307 308 reset-gpios = <&pio 33 0>; 309 310 core-supply = <&mt6323_vpa_reg>; 311 io-supply = <&mt6323_vemc3v3_reg>; 312 313 ethernet-ports { 314 #address-cells = <1>; 315 #size-cells = <0>; 316 317 port@0 { 318 reg = <0>; 319 label = "lan1"; 320 }; 321 322 port@1 { 323 reg = <1>; 324 label = "lan2"; 325 }; 326 327 port@2 { 328 reg = <2>; 329 label = "lan3"; 330 }; 331 332 port@3 { 333 reg = <3>; 334 label = "lan4"; 335 }; 336 337 port@4 { 338 reg = <4>; 339 label = "wan"; 340 }; 341 342 port@6 { 343 reg = <6>; 344 ethernet = <&gmac0>; 345 phy-mode = "rgmii"; 346 347 fixed-link { 348 speed = <1000>; 349 full-duplex; 350 pause; 351 }; 352 }; 353 }; 354 }; 355 }; 356 357 # Example 2: MT7530 in MT7623AI SoC 358 - | 359 #include <dt-bindings/reset/mt2701-resets.h> 360 361 mdio { 362 #address-cells = <1>; 363 #size-cells = <0>; 364 365 switch@1f { 366 compatible = "mediatek,mt7530"; 367 reg = <0x1f>; 368 369 mediatek,mcm; 370 resets = <ðsys MT2701_ETHSYS_MCM_RST>; 371 reset-names = "mcm"; 372 373 core-supply = <&mt6323_vpa_reg>; 374 io-supply = <&mt6323_vemc3v3_reg>; 375 376 ethernet-ports { 377 #address-cells = <1>; 378 #size-cells = <0>; 379 380 port@0 { 381 reg = <0>; 382 label = "lan1"; 383 }; 384 385 port@1 { 386 reg = <1>; 387 label = "lan2"; 388 }; 389 390 port@2 { 391 reg = <2>; 392 label = "lan3"; 393 }; 394 395 port@3 { 396 reg = <3>; 397 label = "lan4"; 398 }; 399 400 port@4 { 401 reg = <4>; 402 label = "wan"; 403 }; 404 405 port@6 { 406 reg = <6>; 407 ethernet = <&gmac0>; 408 phy-mode = "trgmii"; 409 410 fixed-link { 411 speed = <1000>; 412 full-duplex; 413 pause; 414 }; 415 }; 416 }; 417 }; 418 }; 419 420 # Example 3: Standalone MT7531 421 - | 422 #include <dt-bindings/gpio/gpio.h> 423 #include <dt-bindings/interrupt-controller/irq.h> 424 425 mdio { 426 #address-cells = <1>; 427 #size-cells = <0>; 428 429 switch@0 { 430 compatible = "mediatek,mt7531"; 431 reg = <0>; 432 433 reset-gpios = <&pio 54 0>; 434 435 interrupt-controller; 436 #interrupt-cells = <1>; 437 interrupt-parent = <&pio>; 438 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; 439 440 ethernet-ports { 441 #address-cells = <1>; 442 #size-cells = <0>; 443 444 port@0 { 445 reg = <0>; 446 label = "lan1"; 447 }; 448 449 port@1 { 450 reg = <1>; 451 label = "lan2"; 452 }; 453 454 port@2 { 455 reg = <2>; 456 label = "lan3"; 457 }; 458 459 port@3 { 460 reg = <3>; 461 label = "lan4"; 462 }; 463 464 port@4 { 465 reg = <4>; 466 label = "wan"; 467 }; 468 469 port@6 { 470 reg = <6>; 471 ethernet = <&gmac0>; 472 phy-mode = "2500base-x"; 473 474 fixed-link { 475 speed = <2500>; 476 full-duplex; 477 pause; 478 }; 479 }; 480 }; 481 }; 482 }; 483 484 # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs 485 - | 486 #include <dt-bindings/interrupt-controller/mips-gic.h> 487 #include <dt-bindings/reset/mt7621-reset.h> 488 489 mdio { 490 #address-cells = <1>; 491 #size-cells = <0>; 492 493 switch@1f { 494 compatible = "mediatek,mt7621"; 495 reg = <0x1f>; 496 497 mediatek,mcm; 498 resets = <&sysc MT7621_RST_MCM>; 499 reset-names = "mcm"; 500 501 interrupt-controller; 502 #interrupt-cells = <1>; 503 interrupt-parent = <&gic>; 504 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 505 506 ethernet-ports { 507 #address-cells = <1>; 508 #size-cells = <0>; 509 510 port@0 { 511 reg = <0>; 512 label = "lan1"; 513 }; 514 515 port@1 { 516 reg = <1>; 517 label = "lan2"; 518 }; 519 520 port@2 { 521 reg = <2>; 522 label = "lan3"; 523 }; 524 525 port@3 { 526 reg = <3>; 527 label = "lan4"; 528 }; 529 530 port@4 { 531 reg = <4>; 532 label = "wan"; 533 }; 534 535 port@6 { 536 reg = <6>; 537 ethernet = <&gmac0>; 538 phy-mode = "trgmii"; 539 540 fixed-link { 541 speed = <1000>; 542 full-duplex; 543 pause; 544 }; 545 }; 546 }; 547 }; 548 }; 549 550 # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 551 - | 552 #include <dt-bindings/interrupt-controller/mips-gic.h> 553 #include <dt-bindings/reset/mt7621-reset.h> 554 555 ethernet { 556 #address-cells = <1>; 557 #size-cells = <0>; 558 559 pinctrl-names = "default"; 560 pinctrl-0 = <&rgmii2_pins>; 561 562 mac@1 { 563 compatible = "mediatek,eth-mac"; 564 reg = <1>; 565 566 phy-mode = "rgmii"; 567 phy-handle = <&example5_ethphy4>; 568 }; 569 570 mdio { 571 #address-cells = <1>; 572 #size-cells = <0>; 573 574 /* MT7530's phy4 */ 575 example5_ethphy4: ethernet-phy@4 { 576 reg = <4>; 577 }; 578 579 switch@1f { 580 compatible = "mediatek,mt7621"; 581 reg = <0x1f>; 582 583 mediatek,mcm; 584 resets = <&sysc MT7621_RST_MCM>; 585 reset-names = "mcm"; 586 587 interrupt-controller; 588 #interrupt-cells = <1>; 589 interrupt-parent = <&gic>; 590 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 591 592 ethernet-ports { 593 #address-cells = <1>; 594 #size-cells = <0>; 595 596 port@0 { 597 reg = <0>; 598 label = "lan1"; 599 }; 600 601 port@1 { 602 reg = <1>; 603 label = "lan2"; 604 }; 605 606 port@2 { 607 reg = <2>; 608 label = "lan3"; 609 }; 610 611 port@3 { 612 reg = <3>; 613 label = "lan4"; 614 }; 615 616 /* Commented out, phy4 is connected to gmac1. 617 port@4 { 618 reg = <4>; 619 label = "wan"; 620 }; 621 */ 622 623 port@6 { 624 reg = <6>; 625 ethernet = <&gmac0>; 626 phy-mode = "trgmii"; 627 628 fixed-link { 629 speed = <1000>; 630 full-duplex; 631 pause; 632 }; 633 }; 634 }; 635 }; 636 }; 637 }; 638 639 # Example 6: MT7621: mux external phy to SoC's gmac1 640 - | 641 #include <dt-bindings/interrupt-controller/mips-gic.h> 642 #include <dt-bindings/reset/mt7621-reset.h> 643 644 ethernet { 645 #address-cells = <1>; 646 #size-cells = <0>; 647 648 pinctrl-names = "default"; 649 pinctrl-0 = <&rgmii2_pins>; 650 651 mac@1 { 652 compatible = "mediatek,eth-mac"; 653 reg = <1>; 654 655 phy-mode = "rgmii"; 656 phy-handle = <&example6_ethphy7>; 657 }; 658 659 mdio { 660 #address-cells = <1>; 661 #size-cells = <0>; 662 663 /* External PHY */ 664 example6_ethphy7: ethernet-phy@7 { 665 reg = <7>; 666 phy-mode = "rgmii"; 667 }; 668 669 switch@1f { 670 compatible = "mediatek,mt7621"; 671 reg = <0x1f>; 672 673 mediatek,mcm; 674 resets = <&sysc MT7621_RST_MCM>; 675 reset-names = "mcm"; 676 677 interrupt-controller; 678 #interrupt-cells = <1>; 679 interrupt-parent = <&gic>; 680 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 681 682 ethernet-ports { 683 #address-cells = <1>; 684 #size-cells = <0>; 685 686 port@0 { 687 reg = <0>; 688 label = "lan1"; 689 }; 690 691 port@1 { 692 reg = <1>; 693 label = "lan2"; 694 }; 695 696 port@2 { 697 reg = <2>; 698 label = "lan3"; 699 }; 700 701 port@3 { 702 reg = <3>; 703 label = "lan4"; 704 }; 705 706 port@4 { 707 reg = <4>; 708 label = "wan"; 709 }; 710 711 port@6 { 712 reg = <6>; 713 ethernet = <&gmac0>; 714 phy-mode = "trgmii"; 715 716 fixed-link { 717 speed = <1000>; 718 full-duplex; 719 pause; 720 }; 721 }; 722 }; 723 }; 724 }; 725 }; 726 727 # Example 7: MT7621: mux external phy to MT7530's port 5 728 - | 729 #include <dt-bindings/interrupt-controller/mips-gic.h> 730 #include <dt-bindings/reset/mt7621-reset.h> 731 732 ethernet { 733 #address-cells = <1>; 734 #size-cells = <0>; 735 736 pinctrl-names = "default"; 737 pinctrl-0 = <&rgmii2_pins>; 738 739 mdio { 740 #address-cells = <1>; 741 #size-cells = <0>; 742 743 /* External PHY */ 744 example7_ethphy7: ethernet-phy@7 { 745 reg = <7>; 746 phy-mode = "rgmii"; 747 }; 748 749 switch@1f { 750 compatible = "mediatek,mt7621"; 751 reg = <0x1f>; 752 753 mediatek,mcm; 754 resets = <&sysc MT7621_RST_MCM>; 755 reset-names = "mcm"; 756 757 interrupt-controller; 758 #interrupt-cells = <1>; 759 interrupt-parent = <&gic>; 760 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 761 762 ethernet-ports { 763 #address-cells = <1>; 764 #size-cells = <0>; 765 766 port@0 { 767 reg = <0>; 768 label = "lan1"; 769 }; 770 771 port@1 { 772 reg = <1>; 773 label = "lan2"; 774 }; 775 776 port@2 { 777 reg = <2>; 778 label = "lan3"; 779 }; 780 781 port@3 { 782 reg = <3>; 783 label = "lan4"; 784 }; 785 786 port@4 { 787 reg = <4>; 788 label = "wan"; 789 }; 790 791 port@5 { 792 reg = <5>; 793 label = "extphy"; 794 phy-mode = "rgmii-txid"; 795 phy-handle = <&example7_ethphy7>; 796 }; 797 798 port@6 { 799 reg = <6>; 800 ethernet = <&gmac0>; 801 phy-mode = "trgmii"; 802 803 fixed-link { 804 speed = <1000>; 805 full-duplex; 806 pause; 807 }; 808 }; 809 }; 810 }; 811 }; 812 }; 813