xref: /freebsd/sys/contrib/device-tree/Bindings/net/dsa/lantiq-gswip.txt (revision dd41de95a84d979615a2ef11df6850622bf6184e) 
1Lantiq GSWIP Ethernet switches
2==================================
3
4Required properties for GSWIP core:
5
6- compatible	: "lantiq,xrx200-gswip" for the embedded GSWIP in the
7		  xRX200 SoC
8- reg		: memory range of the GSWIP core registers
9		: memory range of the GSWIP MDIO registers
10		: memory range of the GSWIP MII registers
11
12See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of
13additional required and optional properties.
14
15
16Required properties for MDIO bus:
17- compatible	: "lantiq,xrx200-mdio" for the MDIO bus inside the GSWIP
18		  core of the xRX200 SoC and the PHYs connected to it.
19
20See Documentation/devicetree/bindings/net/mdio.txt for a list of additional
21required and optional properties.
22
23
24Required properties for GPHY firmware loading:
25- compatible	: "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw"
26		  "lantiq,xrx300-gphy-fw", "lantiq,gphy-fw"
27		  "lantiq,xrx330-gphy-fw", "lantiq,gphy-fw"
28		  for the loading of the firmware into the embedded
29		  GPHY core of the SoC.
30- lantiq,rcu	: reference to the rcu syscon
31
32The GPHY firmware loader has a list of GPHY entries, one for each
33embedded GPHY
34
35- reg		: Offset of the GPHY firmware register in the RCU
36		  register range
37- resets	: list of resets of the embedded GPHY
38- reset-names	: list of names of the resets
39
40Example:
41
42Ethernet switch on the VRX200 SoC:
43
44switch@e108000 {
45	#address-cells = <1>;
46	#size-cells = <0>;
47	compatible = "lantiq,xrx200-gswip";
48	reg = <	0xe108000 0x3100	/* switch */
49		0xe10b100 0xd8		/* mdio */
50		0xe10b1d8 0x130		/* mii */
51		>;
52	dsa,member = <0 0>;
53
54	ports {
55		#address-cells = <1>;
56		#size-cells = <0>;
57
58		port@0 {
59			reg = <0>;
60			label = "lan3";
61			phy-mode = "rgmii";
62			phy-handle = <&phy0>;
63		};
64
65		port@1 {
66			reg = <1>;
67			label = "lan4";
68			phy-mode = "rgmii";
69			phy-handle = <&phy1>;
70		};
71
72		port@2 {
73			reg = <2>;
74			label = "lan2";
75			phy-mode = "internal";
76			phy-handle = <&phy11>;
77		};
78
79		port@4 {
80			reg = <4>;
81			label = "lan1";
82			phy-mode = "internal";
83			phy-handle = <&phy13>;
84		};
85
86		port@5 {
87			reg = <5>;
88			label = "wan";
89			phy-mode = "rgmii";
90			phy-handle = <&phy5>;
91		};
92
93		port@6 {
94			reg = <0x6>;
95			label = "cpu";
96			ethernet = <&eth0>;
97		};
98	};
99
100	mdio {
101		#address-cells = <1>;
102		#size-cells = <0>;
103		compatible = "lantiq,xrx200-mdio";
104		reg = <0>;
105
106		phy0: ethernet-phy@0 {
107			reg = <0x0>;
108		};
109		phy1: ethernet-phy@1 {
110			reg = <0x1>;
111		};
112		phy5: ethernet-phy@5 {
113			reg = <0x5>;
114		};
115		phy11: ethernet-phy@11 {
116			reg = <0x11>;
117		};
118		phy13: ethernet-phy@13 {
119			reg = <0x13>;
120		};
121	};
122
123	gphy-fw {
124		compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
125		lantiq,rcu = <&rcu0>;
126		#address-cells = <1>;
127		#size-cells = <0>;
128
129		gphy@20 {
130			reg = <0x20>;
131
132			resets = <&reset0 31 30>;
133			reset-names = "gphy";
134		};
135
136		gphy@68 {
137			reg = <0x68>;
138
139			resets = <&reset0 29 28>;
140			reset-names = "gphy";
141		};
142	};
143};
144