1Atheros AR9331 built-in switch 2============================= 3 4It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal 5MDIO bus. All PHYs are built-in as well. 6 7Required properties: 8 9 - compatible: should be: "qca,ar9331-switch" 10 - reg: Address on the MII bus for the switch. 11 - resets : Must contain an entry for each entry in reset-names. 12 - reset-names : Must include the following entries: "switch" 13 - interrupt-parent: Phandle to the parent interrupt controller 14 - interrupts: IRQ line for the switch 15 - interrupt-controller: Indicates the switch is itself an interrupt 16 controller. This is used for the PHY interrupts. 17 - #interrupt-cells: must be 1 18 - mdio: Container of PHY and devices on the switches MDIO bus. 19 20See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional 21required and optional properties. 22Examples: 23 24eth0: ethernet@19000000 { 25 compatible = "qca,ar9330-eth"; 26 reg = <0x19000000 0x200>; 27 interrupts = <4>; 28 29 resets = <&rst 9>, <&rst 22>; 30 reset-names = "mac", "mdio"; 31 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; 32 clock-names = "eth", "mdio"; 33 34 phy-mode = "mii"; 35 phy-handle = <&phy_port4>; 36}; 37 38eth1: ethernet@1a000000 { 39 compatible = "qca,ar9330-eth"; 40 reg = <0x1a000000 0x200>; 41 interrupts = <5>; 42 resets = <&rst 13>, <&rst 23>; 43 reset-names = "mac", "mdio"; 44 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; 45 clock-names = "eth", "mdio"; 46 47 phy-mode = "gmii"; 48 49 fixed-link { 50 speed = <1000>; 51 full-duplex; 52 }; 53 54 mdio { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 switch10: switch@10 { 59 #address-cells = <1>; 60 #size-cells = <0>; 61 62 compatible = "qca,ar9331-switch"; 63 reg = <0x10>; 64 resets = <&rst 8>; 65 reset-names = "switch"; 66 67 interrupt-parent = <&miscintc>; 68 interrupts = <12>; 69 70 interrupt-controller; 71 #interrupt-cells = <1>; 72 73 ports { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 switch_port0: port@0 { 78 reg = <0x0>; 79 label = "cpu"; 80 ethernet = <ð1>; 81 82 phy-mode = "gmii"; 83 84 fixed-link { 85 speed = <1000>; 86 full-duplex; 87 }; 88 }; 89 90 switch_port1: port@1 { 91 reg = <0x1>; 92 phy-handle = <&phy_port0>; 93 phy-mode = "internal"; 94 }; 95 96 switch_port2: port@2 { 97 reg = <0x2>; 98 phy-handle = <&phy_port1>; 99 phy-mode = "internal"; 100 }; 101 102 switch_port3: port@3 { 103 reg = <0x3>; 104 phy-handle = <&phy_port2>; 105 phy-mode = "internal"; 106 }; 107 108 switch_port4: port@4 { 109 reg = <0x4>; 110 phy-handle = <&phy_port3>; 111 phy-mode = "internal"; 112 }; 113 }; 114 115 mdio { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 interrupt-parent = <&switch10>; 120 121 phy_port0: phy@0 { 122 reg = <0x0>; 123 interrupts = <0>; 124 }; 125 126 phy_port1: phy@1 { 127 reg = <0x1>; 128 interrupts = <0>; 129 }; 130 131 phy_port2: phy@2 { 132 reg = <0x2>; 133 interrupts = <0>; 134 }; 135 136 phy_port3: phy@3 { 137 reg = <0x3>; 138 interrupts = <0>; 139 }; 140 141 phy_port4: phy@4 { 142 reg = <0x4>; 143 interrupts = <0>; 144 }; 145 }; 146 }; 147 }; 148}; 149