1Atheros AR9331 built-in switch 2============================= 3 4It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal 5MDIO bus. All PHYs are built-in as well. 6 7Required properties: 8 9 - compatible: should be: "qca,ar9331-switch" 10 - reg: Address on the MII bus for the switch. 11 - resets : Must contain an entry for each entry in reset-names. 12 - reset-names : Must include the following entries: "switch" 13 - interrupt-parent: Phandle to the parent interrupt controller 14 - interrupts: IRQ line for the switch 15 - interrupt-controller: Indicates the switch is itself an interrupt 16 controller. This is used for the PHY interrupts. 17 - #interrupt-cells: must be 1 18 - mdio: Container of PHY and devices on the switches MDIO bus. 19 20See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional 21required and optional properties. 22Examples: 23 24eth0: ethernet@19000000 { 25 compatible = "qca,ar9330-eth"; 26 reg = <0x19000000 0x200>; 27 interrupts = <4>; 28 29 resets = <&rst 9>, <&rst 22>; 30 reset-names = "mac", "mdio"; 31 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; 32 clock-names = "eth", "mdio"; 33 34 phy-mode = "mii"; 35 phy-handle = <&phy_port4>; 36}; 37 38eth1: ethernet@1a000000 { 39 compatible = "qca,ar9330-eth"; 40 reg = <0x1a000000 0x200>; 41 interrupts = <5>; 42 resets = <&rst 13>, <&rst 23>; 43 reset-names = "mac", "mdio"; 44 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; 45 clock-names = "eth", "mdio"; 46 47 phy-mode = "gmii"; 48 49 fixed-link { 50 speed = <1000>; 51 full-duplex; 52 }; 53 54 mdio { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 switch10: switch@10 { 59 #address-cells = <1>; 60 #size-cells = <0>; 61 62 compatible = "qca,ar9331-switch"; 63 reg = <0x10>; 64 resets = <&rst 8>; 65 reset-names = "switch"; 66 67 interrupt-parent = <&miscintc>; 68 interrupts = <12>; 69 70 interrupt-controller; 71 #interrupt-cells = <1>; 72 73 ports { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 switch_port0: port@0 { 78 reg = <0x0>; 79 ethernet = <ð1>; 80 81 phy-mode = "gmii"; 82 83 fixed-link { 84 speed = <1000>; 85 full-duplex; 86 }; 87 }; 88 89 switch_port1: port@1 { 90 reg = <0x1>; 91 phy-handle = <&phy_port0>; 92 phy-mode = "internal"; 93 }; 94 95 switch_port2: port@2 { 96 reg = <0x2>; 97 phy-handle = <&phy_port1>; 98 phy-mode = "internal"; 99 }; 100 101 switch_port3: port@3 { 102 reg = <0x3>; 103 phy-handle = <&phy_port2>; 104 phy-mode = "internal"; 105 }; 106 107 switch_port4: port@4 { 108 reg = <0x4>; 109 phy-handle = <&phy_port3>; 110 phy-mode = "internal"; 111 }; 112 }; 113 114 mdio { 115 #address-cells = <1>; 116 #size-cells = <0>; 117 118 interrupt-parent = <&switch10>; 119 120 phy_port0: phy@0 { 121 reg = <0x0>; 122 interrupts = <0>; 123 }; 124 125 phy_port1: phy@1 { 126 reg = <0x1>; 127 interrupts = <0>; 128 }; 129 130 phy_port2: phy@2 { 131 reg = <0x2>; 132 interrupts = <0>; 133 }; 134 135 phy_port3: phy@3 { 136 reg = <0x3>; 137 interrupts = <0>; 138 }; 139 140 phy_port4: phy@4 { 141 reg = <0x4>; 142 interrupts = <0>; 143 }; 144 }; 145 }; 146 }; 147}; 148