1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/can/renesas,rcar-canfd.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas R-Car CAN FD Controller 8 9maintainers: 10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com> 11 12allOf: 13 - $ref: can-controller.yaml# 14 15properties: 16 compatible: 17 oneOf: 18 - items: 19 - enum: 20 - renesas,r8a774a1-canfd # RZ/G2M 21 - renesas,r8a774b1-canfd # RZ/G2N 22 - renesas,r8a774c0-canfd # RZ/G2E 23 - renesas,r8a774e1-canfd # RZ/G2H 24 - renesas,r8a7795-canfd # R-Car H3 25 - renesas,r8a7796-canfd # R-Car M3-W 26 - renesas,r8a77961-canfd # R-Car M3-W+ 27 - renesas,r8a77965-canfd # R-Car M3-N 28 - renesas,r8a77970-canfd # R-Car V3M 29 - renesas,r8a77980-canfd # R-Car V3H 30 - renesas,r8a77990-canfd # R-Car E3 31 - renesas,r8a77995-canfd # R-Car D3 32 - const: renesas,rcar-gen3-canfd # R-Car Gen3 and RZ/G2 33 34 - items: 35 - enum: 36 - renesas,r9a07g043-canfd # RZ/G2UL 37 - renesas,r9a07g044-canfd # RZ/G2{L,LC} 38 - renesas,r9a07g054-canfd # RZ/V2L 39 - const: renesas,rzg2l-canfd # RZ/G2L family 40 41 - const: renesas,r8a779a0-canfd # R-Car V3U 42 43 reg: 44 maxItems: 1 45 46 interrupts: true 47 48 clocks: 49 maxItems: 3 50 51 clock-names: 52 items: 53 - const: fck 54 - const: canfd 55 - const: can_clk 56 57 power-domains: 58 maxItems: 1 59 60 resets: true 61 62 renesas,no-can-fd: 63 $ref: /schemas/types.yaml#/definitions/flag 64 description: 65 The controller can operate in either CAN FD only mode (default) or 66 Classical CAN only mode. The mode is global to both the channels. 67 Specify this property to put the controller in Classical CAN only mode. 68 69 assigned-clocks: 70 description: 71 Reference to the CANFD clock. The CANFD clock is a div6 clock and can be 72 used by both CAN (if present) and CAN FD controllers at the same time. 73 It needs to be scaled to maximum frequency if any of these controllers 74 use it. 75 76 assigned-clock-rates: 77 description: Maximum frequency of the CANFD clock. 78 79patternProperties: 80 "^channel[01]$": 81 type: object 82 description: 83 The controller supports two channels and each is represented as a child 84 node. Each child node supports the "status" property only, which 85 is used to enable/disable the respective channel. 86 87required: 88 - compatible 89 - reg 90 - interrupts 91 - interrupt-names 92 - clocks 93 - clock-names 94 - power-domains 95 - resets 96 - assigned-clocks 97 - assigned-clock-rates 98 - channel0 99 - channel1 100 101if: 102 properties: 103 compatible: 104 contains: 105 enum: 106 - renesas,rzg2l-canfd 107then: 108 properties: 109 interrupts: 110 items: 111 - description: CAN global error interrupt 112 - description: CAN receive FIFO interrupt 113 - description: CAN0 error interrupt 114 - description: CAN0 transmit interrupt 115 - description: CAN0 transmit/receive FIFO receive completion interrupt 116 - description: CAN1 error interrupt 117 - description: CAN1 transmit interrupt 118 - description: CAN1 transmit/receive FIFO receive completion interrupt 119 120 interrupt-names: 121 items: 122 - const: g_err 123 - const: g_recc 124 - const: ch0_err 125 - const: ch0_rec 126 - const: ch0_trx 127 - const: ch1_err 128 - const: ch1_rec 129 - const: ch1_trx 130 131 resets: 132 maxItems: 2 133 134 reset-names: 135 items: 136 - const: rstp_n 137 - const: rstc_n 138 139 required: 140 - reset-names 141else: 142 properties: 143 interrupts: 144 items: 145 - description: Channel interrupt 146 - description: Global interrupt 147 148 interrupt-names: 149 items: 150 - const: ch_int 151 - const: g_int 152 153 resets: 154 maxItems: 1 155 156unevaluatedProperties: false 157 158examples: 159 - | 160 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 161 #include <dt-bindings/interrupt-controller/arm-gic.h> 162 #include <dt-bindings/power/r8a7795-sysc.h> 163 164 canfd: can@e66c0000 { 165 compatible = "renesas,r8a7795-canfd", 166 "renesas,rcar-gen3-canfd"; 167 reg = <0xe66c0000 0x8000>; 168 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 170 interrupt-names = "ch_int", "g_int"; 171 clocks = <&cpg CPG_MOD 914>, 172 <&cpg CPG_CORE R8A7795_CLK_CANFD>, 173 <&can_clk>; 174 clock-names = "fck", "canfd", "can_clk"; 175 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 176 assigned-clock-rates = <40000000>; 177 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 178 resets = <&cpg 914>; 179 180 channel0 { 181 }; 182 183 channel1 { 184 }; 185 }; 186