1Renesas R-Car CAN FD controller Device Tree Bindings 2---------------------------------------------------- 3 4Required properties: 5- compatible: Must contain one or more of the following: 6 - "renesas,rcar-gen3-canfd" for R-Car Gen3 and RZ/G2 compatible controllers. 7 - "renesas,r8a774a1-canfd" for R8A774A1 (RZ/G2M) compatible controller. 8 - "renesas,r8a774b1-canfd" for R8A774B1 (RZ/G2N) compatible controller. 9 - "renesas,r8a774c0-canfd" for R8A774C0 (RZ/G2E) compatible controller. 10 - "renesas,r8a774e1-canfd" for R8A774E1 (RZ/G2H) compatible controller. 11 - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller. 12 - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller. 13 - "renesas,r8a77965-canfd" for R8A77965 (R-Car M3-N) compatible controller. 14 - "renesas,r8a77970-canfd" for R8A77970 (R-Car V3M) compatible controller. 15 - "renesas,r8a77980-canfd" for R8A77980 (R-Car V3H) compatible controller. 16 - "renesas,r8a77990-canfd" for R8A77990 (R-Car E3) compatible controller. 17 - "renesas,r8a77995-canfd" for R8A77995 (R-Car D3) compatible controller. 18 19 When compatible with the generic version, nodes must list the 20 SoC-specific version corresponding to the platform first, followed by the 21 family-specific and/or generic versions. 22 23- reg: physical base address and size of the R-Car CAN FD register map. 24- interrupts: interrupt specifiers for the Channel & Global interrupts 25- clocks: phandles and clock specifiers for 3 clock inputs. 26- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk". 27- pinctrl-0: pin control group to be used for this controller. 28- pinctrl-names: must be "default". 29 30Required child nodes: 31The controller supports two channels and each is represented as a child node. 32The name of the child nodes are "channel0" and "channel1" respectively. Each 33child node supports the "status" property only, which is used to 34enable/disable the respective channel. 35 36Required properties for R8A774A1, R8A774B1, R8A774C0, R8A774E1, R8A7795, 37R8A7796, R8A77965, R8A77990, and R8A77995: 38In the denoted SoCs, canfd clock is a div6 clock and can be used by both CAN 39and CAN FD controller at the same time. It needs to be scaled to maximum 40frequency if any of these controllers use it. This is done using the below 41properties: 42 43- assigned-clocks: phandle of canfd clock. 44- assigned-clock-rates: maximum frequency of this clock. 45 46Optional property: 47The controller can operate in either CAN FD only mode (default) or 48Classical CAN only mode. The mode is global to both the channels. In order to 49enable the later, define the following optional property. 50 - renesas,no-can-fd: puts the controller in Classical CAN only mode. 51 52Example 53------- 54 55SoC common .dtsi file: 56 57 canfd: can@e66c0000 { 58 compatible = "renesas,r8a7795-canfd", 59 "renesas,rcar-gen3-canfd"; 60 reg = <0 0xe66c0000 0 0x8000>; 61 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 63 clocks = <&cpg CPG_MOD 914>, 64 <&cpg CPG_CORE R8A7795_CLK_CANFD>, 65 <&can_clk>; 66 clock-names = "fck", "canfd", "can_clk"; 67 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 68 assigned-clock-rates = <40000000>; 69 power-domains = <&cpg>; 70 status = "disabled"; 71 72 channel0 { 73 status = "disabled"; 74 }; 75 76 channel1 { 77 status = "disabled"; 78 }; 79 }; 80 81Board specific .dts file: 82 83E.g. below enables Channel 1 alone in the board in Classical CAN only mode. 84 85&canfd { 86 pinctrl-0 = <&canfd1_pins>; 87 pinctrl-names = "default"; 88 renesas,no-can-fd; 89 status = "okay"; 90 91 channel1 { 92 status = "okay"; 93 }; 94}; 95 96E.g. below enables Channel 0 alone in the board using External clock 97as fCAN clock. 98 99&canfd { 100 pinctrl-0 = <&canfd0_pins>, <&can_clk_pins>; 101 pinctrl-names = "default"; 102 status = "okay"; 103 104 channel0 { 105 status = "okay"; 106 }; 107}; 108