1Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC). 2 3Required properties: 4 5- compatible : Should be "fsl,<processor>-flexcan" 6 7 An implementation should also claim any of the following compatibles 8 that it is fully backwards compatible with: 9 10 - fsl,p1010-flexcan 11 12- reg : Offset and length of the register set for this device 13- interrupts : Interrupt tuple for this device 14 15Optional properties: 16 17- clock-frequency : The oscillator frequency driving the flexcan device 18 19- xceiver-supply: Regulator that powers the CAN transceiver 20 21- big-endian: This means the registers of FlexCAN controller are big endian. 22 This is optional property.i.e. if this property is not present in 23 device tree node then controller is assumed to be little endian. 24 if this property is present then controller is assumed to be big 25 endian. 26 27- fsl,stop-mode: register bits of stop mode control, the format is 28 <&gpr req_gpr req_bit ack_gpr ack_bit>. 29 gpr is the phandle to general purpose register node. 30 req_gpr is the gpr register offset of CAN stop request. 31 req_bit is the bit offset of CAN stop request. 32 ack_gpr is the gpr register offset of CAN stop acknowledge. 33 ack_bit is the bit offset of CAN stop acknowledge. 34 35- fsl,clk-source: Select the clock source to the CAN Protocol Engine (PE). 36 It's SoC Implementation dependent. Refer to RM for detailed 37 definition. If this property is not set in device tree node 38 then driver selects clock source 1 by default. 39 0: clock source 0 (oscillator clock) 40 1: clock source 1 (peripheral clock) 41 42- wakeup-source: enable CAN remote wakeup 43 44Example: 45 46 can@1c000 { 47 compatible = "fsl,p1010-flexcan"; 48 reg = <0x1c000 0x1000>; 49 interrupts = <48 0x2>; 50 interrupt-parent = <&mpic>; 51 clock-frequency = <200000000>; // filled in by bootloader 52 fsl,clk-source = <0>; // select clock source 0 for PE 53 }; 54