1*d5b0e70fSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*d5b0e70fSEmmanuel Vadot%YAML 1.2 3*d5b0e70fSEmmanuel Vadot--- 4*d5b0e70fSEmmanuel Vadot$id: http://devicetree.org/schemas/net/can/ctu,ctucanfd.yaml# 5*d5b0e70fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*d5b0e70fSEmmanuel Vadot 7*d5b0e70fSEmmanuel Vadottitle: CTU CAN FD Open-source IP Core Device Tree Bindings 8*d5b0e70fSEmmanuel Vadot 9*d5b0e70fSEmmanuel Vadotdescription: | 10*d5b0e70fSEmmanuel Vadot Open-source CAN FD IP core developed at the Czech Technical University in Prague 11*d5b0e70fSEmmanuel Vadot 12*d5b0e70fSEmmanuel Vadot The core sources and documentation on project page 13*d5b0e70fSEmmanuel Vadot [1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core 14*d5b0e70fSEmmanuel Vadot [2] datasheet : https://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/Datasheet.pdf 15*d5b0e70fSEmmanuel Vadot 16*d5b0e70fSEmmanuel Vadot Integration in Xilinx Zynq SoC based system together with 17*d5b0e70fSEmmanuel Vadot OpenCores SJA1000 compatible controllers 18*d5b0e70fSEmmanuel Vadot [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top 19*d5b0e70fSEmmanuel Vadot Martin Jerabek dimploma thesis with integration and testing 20*d5b0e70fSEmmanuel Vadot framework description 21*d5b0e70fSEmmanuel Vadot [4] PDF : https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-canfd.pdf 22*d5b0e70fSEmmanuel Vadot 23*d5b0e70fSEmmanuel Vadotmaintainers: 24*d5b0e70fSEmmanuel Vadot - Pavel Pisa <pisa@cmp.felk.cvut.cz> 25*d5b0e70fSEmmanuel Vadot - Ondrej Ille <ondrej.ille@gmail.com> 26*d5b0e70fSEmmanuel Vadot - Martin Jerabek <martin.jerabek01@gmail.com> 27*d5b0e70fSEmmanuel Vadot 28*d5b0e70fSEmmanuel VadotallOf: 29*d5b0e70fSEmmanuel Vadot - $ref: can-controller.yaml# 30*d5b0e70fSEmmanuel Vadot 31*d5b0e70fSEmmanuel Vadotproperties: 32*d5b0e70fSEmmanuel Vadot compatible: 33*d5b0e70fSEmmanuel Vadot oneOf: 34*d5b0e70fSEmmanuel Vadot - items: 35*d5b0e70fSEmmanuel Vadot - const: ctu,ctucanfd-2 36*d5b0e70fSEmmanuel Vadot - const: ctu,ctucanfd 37*d5b0e70fSEmmanuel Vadot - const: ctu,ctucanfd 38*d5b0e70fSEmmanuel Vadot 39*d5b0e70fSEmmanuel Vadot reg: 40*d5b0e70fSEmmanuel Vadot maxItems: 1 41*d5b0e70fSEmmanuel Vadot 42*d5b0e70fSEmmanuel Vadot interrupts: 43*d5b0e70fSEmmanuel Vadot maxItems: 1 44*d5b0e70fSEmmanuel Vadot 45*d5b0e70fSEmmanuel Vadot clocks: 46*d5b0e70fSEmmanuel Vadot description: | 47*d5b0e70fSEmmanuel Vadot phandle of reference clock (100 MHz is appropriate 48*d5b0e70fSEmmanuel Vadot for FPGA implementation on Zynq-7000 system). 49*d5b0e70fSEmmanuel Vadot maxItems: 1 50*d5b0e70fSEmmanuel Vadot 51*d5b0e70fSEmmanuel Vadotrequired: 52*d5b0e70fSEmmanuel Vadot - compatible 53*d5b0e70fSEmmanuel Vadot - reg 54*d5b0e70fSEmmanuel Vadot - interrupts 55*d5b0e70fSEmmanuel Vadot - clocks 56*d5b0e70fSEmmanuel Vadot 57*d5b0e70fSEmmanuel VadotadditionalProperties: false 58*d5b0e70fSEmmanuel Vadot 59*d5b0e70fSEmmanuel Vadotexamples: 60*d5b0e70fSEmmanuel Vadot - | 61*d5b0e70fSEmmanuel Vadot ctu_can_fd_0: can@43c30000 { 62*d5b0e70fSEmmanuel Vadot compatible = "ctu,ctucanfd"; 63*d5b0e70fSEmmanuel Vadot interrupts = <0 30 4>; 64*d5b0e70fSEmmanuel Vadot clocks = <&clkc 15>; 65*d5b0e70fSEmmanuel Vadot reg = <0x43c30000 0x10000>; 66*d5b0e70fSEmmanuel Vadot }; 67