1* Broadcom Starfighter 2 integrated swich 2 3Required properties: 4 5- compatible: should be one of 6 "brcm,bcm7445-switch-v4.0" 7 "brcm,bcm7278-switch-v4.0" 8 "brcm,bcm7278-switch-v4.8" 9- reg: addresses and length of the register sets for the device, must be 6 10 pairs of register addresses and lengths 11- interrupts: interrupts for the devices, must be two interrupts 12- #address-cells: must be 1, see dsa/dsa.txt 13- #size-cells: must be 0, see dsa/dsa.txt 14 15Deprecated binding required properties: 16 17- dsa,mii-bus: phandle to the MDIO bus controller, see dsa/dsa.txt 18- dsa,ethernet: phandle to the CPU network interface controller, see dsa/dsa.txt 19- #address-cells: must be 2, see dsa/dsa.txt 20 21Subnodes: 22 23The integrated switch subnode should be specified according to the binding 24described in dsa/dsa.txt. 25 26Optional properties: 27 28- reg-names: litteral names for the device base register addresses, when present 29 must be: "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" 30 31- interrupt-names: litternal names for the device interrupt lines, when present 32 must be: "switch_0" and "switch_1" 33 34- brcm,num-gphy: specify the maximum number of integrated gigabit PHYs in the 35 switch 36 37- brcm,num-rgmii-ports: specify the maximum number of RGMII interfaces supported 38 by the switch 39 40- brcm,fcb-pause-override: boolean property, if present indicates that the switch 41 supports Failover Control Block pause override capability 42 43- brcm,acb-packets-inflight: boolean property, if present indicates that the switch 44 Admission Control Block supports reporting the number of packets in-flight in a 45 switch queue 46 47- resets: a single phandle and reset identifier pair. See 48 Documentation/devicetree/bindings/reset/reset.txt for details. 49 50- reset-names: If the "reset" property is specified, this property should have 51 the value "switch" to denote the switch reset line. 52 53- clocks: when provided, the first phandle is to the switch's main clock and 54 is valid for both BCM7445 and BCM7278. The second phandle is only applicable 55 to BCM7445 and is to support dividing the switch core clock. 56 57- clock-names: when provided, the first phandle must be "sw_switch", and the 58 second must be named "sw_switch_mdiv". 59 60Port subnodes: 61 62Optional properties: 63 64- brcm,use-bcm-hdr: boolean property, if present, indicates that the switch 65 port has Broadcom tags enabled (per-packet metadata) 66 67Example: 68 69switch_top@f0b00000 { 70 compatible = "simple-bus"; 71 #size-cells = <1>; 72 #address-cells = <1>; 73 ranges = <0 0xf0b00000 0x40804>; 74 75 ethernet_switch@0 { 76 compatible = "brcm,bcm7445-switch-v4.0"; 77 #size-cells = <0>; 78 #address-cells = <1>; 79 reg = <0x0 0x40000 80 0x40000 0x110 81 0x40340 0x30 82 0x40380 0x30 83 0x40400 0x34 84 0x40600 0x208>; 85 reg-names = "core", "reg", intrl2_0", "intrl2_1", 86 "fcb, "acb"; 87 interrupts = <0 0x18 0 88 0 0x19 0>; 89 brcm,num-gphy = <1>; 90 brcm,num-rgmii-ports = <2>; 91 brcm,fcb-pause-override; 92 brcm,acb-packets-inflight; 93 94 ports { 95 #address-cells = <1>; 96 #size-cells = <0>; 97 98 port@0 { 99 label = "gphy"; 100 reg = <0>; 101 }; 102 }; 103 }; 104}; 105 106Example using the old DSA DeviceTree binding: 107 108switch_top@f0b00000 { 109 compatible = "simple-bus"; 110 #size-cells = <1>; 111 #address-cells = <1>; 112 ranges = <0 0xf0b00000 0x40804>; 113 114 ethernet_switch@0 { 115 compatible = "brcm,bcm7445-switch-v4.0"; 116 #size-cells = <0>; 117 #address-cells = <2>; 118 reg = <0x0 0x40000 119 0x40000 0x110 120 0x40340 0x30 121 0x40380 0x30 122 0x40400 0x34 123 0x40600 0x208>; 124 interrupts = <0 0x18 0 125 0 0x19 0>; 126 brcm,num-gphy = <1>; 127 brcm,num-rgmii-ports = <2>; 128 brcm,fcb-pause-override; 129 brcm,acb-packets-inflight; 130 131 ... 132 switch@0 { 133 reg = <0 0>; 134 #size-cells = <0>; 135 #address-cells <1>; 136 137 port@0 { 138 label = "gphy"; 139 reg = <0>; 140 brcm,use-bcm-hdr; 141 }; 142 ... 143 }; 144 }; 145}; 146