1Bindings for HyperBus Memory Controller (HBMC) on TI's K3 family of SoCs 2 3Required properties: 4- compatible : "ti,am654-hbmc" for AM654 SoC 5- reg : Two entries: 6 First entry pointed to the register space of HBMC controller 7 Second entry pointing to the memory map region dedicated for 8 MMIO access to attached flash devices 9- ranges : Address translation from offset within CS to allocated MMIO 10 space in SoC 11 12Optional properties: 13- mux-controls : phandle to the multiplexer that controls selection of 14 HBMC vs OSPI inside Flash SubSystem (FSS). Default is OSPI, 15 if property is absent. 16 See Documentation/devicetree/bindings/mux/reg-mux.txt 17 for mmio-mux binding details 18 19Example: 20 21 system-controller@47000000 { 22 compatible = "syscon", "simple-mfd"; 23 reg = <0x0 0x47000000 0x0 0x100>; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 ranges; 27 28 hbmc_mux: multiplexer { 29 compatible = "mmio-mux"; 30 #mux-control-cells = <1>; 31 mux-reg-masks = <0x4 0x2>; /* 0: reg 0x4, bit 1 */ 32 }; 33 }; 34 35 hbmc: hyperbus@47034000 { 36 compatible = "ti,am654-hbmc"; 37 reg = <0x0 0x47034000 0x0 0x100>, 38 <0x5 0x00000000 0x1 0x0000000>; 39 power-domains = <&k3_pds 55>; 40 #address-cells = <2>; 41 #size-cells = <1>; 42 ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */ 43 <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */ 44 mux-controls = <&hbmc_mux 0>; 45 46 /* Slave flash node */ 47 flash@0,0 { 48 compatible = "cypress,hyperflash", "cfi-flash"; 49 reg = <0x0 0x0 0x4000000>; 50 }; 51 }; 52