xref: /freebsd/sys/contrib/device-tree/Bindings/mtd/ti,gpmc-nand.yaml (revision 8cc087a1eee9ec1ca9f7ac1e63ad51bdb5a682eb) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Texas Instruments GPMC NAND Flash controller.
8
9maintainers:
10  - Tony Lindgren <tony@atomide.com>
11  - Roger Quadros <rogerq@kernel.org>
12
13description:
14  GPMC NAND controller/Flash is represented as a child of the
15  GPMC controller node.
16
17properties:
18  compatible:
19    const: ti,omap2-nand
20
21  reg:
22    maxItems: 1
23
24  interrupts:
25    items:
26      - description: Interrupt for fifoevent
27      - description: Interrupt for termcount
28
29  "#address-cells": true
30
31  "#size-cells": true
32
33  ti,nand-ecc-opt:
34    description: Desired ECC algorithm
35    $ref: /schemas/types.yaml#/definitions/string
36    enum: [sw, ham1, bch4, bch8, bch16]
37
38  ti,nand-xfer-type:
39    description: Data transfer method between controller and chip.
40    $ref: /schemas/types.yaml#/definitions/string
41    enum: [prefetch-polled, polled, prefetch-dma, prefetch-irq]
42    default: prefetch-polled
43
44  ti,elm-id:
45    description:
46      phandle to the ELM (Error Location Module).
47    $ref: /schemas/types.yaml#/definitions/phandle
48
49  nand-bus-width:
50    description:
51      Bus width to the NAND chip
52    $ref: /schemas/types.yaml#/definitions/uint32
53    enum: [8, 16]
54    default: 8
55
56patternProperties:
57  "@[0-9a-f]+$":
58    $ref: "/schemas/mtd/partitions/partition.yaml"
59
60allOf:
61  - $ref: "/schemas/memory-controllers/ti,gpmc-child.yaml"
62
63required:
64  - compatible
65  - reg
66  - ti,nand-ecc-opt
67
68unevaluatedProperties: false
69
70examples:
71  - |
72    #include <dt-bindings/interrupt-controller/arm-gic.h>
73    #include <dt-bindings/gpio/gpio.h>
74
75    gpmc: memory-controller@50000000 {
76      compatible = "ti,am3352-gpmc";
77      dmas = <&edma 52 0>;
78      dma-names = "rxtx";
79      clocks = <&l3s_gclk>;
80      clock-names = "fck";
81      reg = <0x50000000 0x2000>;
82      interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
83      gpmc,num-cs = <7>;
84      gpmc,num-waitpins = <2>;
85      #address-cells = <2>;
86      #size-cells = <1>;
87      interrupt-controller;
88      #interrupt-cells = <2>;
89      gpio-controller;
90      #gpio-cells = <2>;
91
92      ranges = <0 0 0x08000000 0x01000000>;   /* CS0 space. Min partition = 16MB */
93      nand@0,0 {
94        compatible = "ti,omap2-nand";
95        reg = <0 0 4>;          /* device IO registers */
96        interrupt-parent = <&gpmc>;
97        interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
98                     <1 IRQ_TYPE_NONE>; /* termcount */
99        ti,nand-xfer-type = "prefetch-dma";
100        ti,nand-ecc-opt = "bch16";
101        ti,elm-id = <&elm>;
102        #address-cells = <1>;
103        #size-cells = <1>;
104
105        /* NAND generic properties */
106        nand-bus-width = <8>;
107        rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;  /* gpmc_wait0 */
108
109        /* GPMC properties*/
110        gpmc,device-width = <1>;
111
112        partition@0 {
113          label = "NAND.SPL";
114          reg = <0x00000000 0x00040000>;
115        };
116        partition@1 {
117          label = "NAND.SPL.backup1";
118          reg = <0x00040000 0x00040000>;
119        };
120      };
121    };
122