1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Raw NAND Chip Common Properties 8 9maintainers: 10 - Miquel Raynal <miquel.raynal@bootlin.com> 11 12allOf: 13 - $ref: nand-chip.yaml# 14 15description: | 16 The ECC strength and ECC step size properties define the user 17 desires in terms of correction capability of a controller. Together, 18 they request the ECC engine to correct {strength} bit errors per 19 {size} bytes for a particular raw NAND chip. 20 21 The interpretation of these parameters is implementation-defined, so 22 not all implementations must support all possible 23 combinations. However, implementations are encouraged to further 24 specify the value(s) they support. 25 26properties: 27 $nodename: 28 pattern: "^nand@[a-f0-9]$" 29 30 reg: 31 description: 32 Contains the chip-select IDs. 33 34 nand-ecc-placement: 35 description: 36 Location of the ECC bytes. This location is unknown by default 37 but can be explicitly set to "oob", if all ECC bytes are 38 known to be stored in the OOB area, or "interleaved" if ECC 39 bytes will be interleaved with regular data in the main area. 40 $ref: /schemas/types.yaml#/definitions/string 41 enum: [ oob, interleaved ] 42 deprecated: true 43 44 nand-ecc-mode: 45 description: 46 Legacy ECC configuration mixing the ECC engine choice and 47 configuration. 48 $ref: /schemas/types.yaml#/definitions/string 49 enum: [none, soft, soft_bch, hw, hw_syndrome, on-die] 50 deprecated: true 51 52 nand-bus-width: 53 description: 54 Bus width to the NAND chip 55 $ref: /schemas/types.yaml#/definitions/uint32 56 enum: [8, 16] 57 default: 8 58 59 nand-on-flash-bbt: 60 description: 61 With this property, the OS will search the device for a Bad 62 Block Table (BBT). If not found, it will create one, reserve 63 a few blocks at the end of the device to store it and update 64 it as the device ages. Otherwise, the out-of-band area of a 65 few pages of all the blocks will be scanned at boot time to 66 find Bad Block Markers (BBM). These markers will help to 67 build a volatile BBT in RAM. 68 $ref: /schemas/types.yaml#/definitions/flag 69 70 nand-ecc-maximize: 71 description: 72 Whether or not the ECC strength should be maximized. The 73 maximum ECC strength is both controller and chip 74 dependent. The ECC engine has to select the ECC config 75 providing the best strength and taking the OOB area size 76 constraint into account. This is particularly useful when 77 only the in-band area is used by the upper layers, and you 78 want to make your NAND as reliable as possible. 79 $ref: /schemas/types.yaml#/definitions/flag 80 81 nand-is-boot-medium: 82 description: 83 Whether or not the NAND chip is a boot medium. Drivers might 84 use this information to select ECC algorithms supported by 85 the boot ROM or similar restrictions. 86 $ref: /schemas/types.yaml#/definitions/flag 87 88 nand-rb: 89 description: 90 Contains the native Ready/Busy IDs. 91 $ref: /schemas/types.yaml#/definitions/uint32-array 92 93 rb-gpios: 94 description: 95 Contains one or more GPIO descriptor (the numper of descriptor 96 depends on the number of R/B pins exposed by the flash) for the 97 Ready/Busy pins. Active state refers to the NAND ready state and 98 should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted. 99 100 wp-gpios: 101 description: 102 Contains one GPIO descriptor for the Write Protect pin. 103 Active state refers to the NAND Write Protect state and should be 104 set to GPIOD_ACTIVE_LOW unless the signal is inverted. 105 maxItems: 1 106 107required: 108 - reg 109 110# This is a generic file other binding inherit from and extend 111additionalProperties: true 112