1* Qualcomm NAND controller 2 3Required properties: 4- compatible: must be one of the following: 5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x 6 SoC and it uses ADM DMA 7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in 8 IPQ4019 SoC and it uses BAM DMA 9 * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in 10 IPQ6018 SoC and it uses BAM DMA 11 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in 12 IPQ8074 SoC and it uses BAM DMA 13 * "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in 14 SDX55 SoC and it uses BAM DMA 15 16- reg: MMIO address range 17- clocks: must contain core clock and always on clock 18- clock-names: must contain "core" for the core clock and "aon" for the 19 always on clock 20 21EBI2 specific properties: 22- dmas: DMA specifier, consisting of a phandle to the ADM DMA 23 controller node and the channel number to be used for 24 NAND. Refer to dma.txt and qcom_adm.txt for more details 25- dma-names: must be "rxtx" 26- qcom,cmd-crci: must contain the ADM command type CRCI block instance 27 number specified for the NAND controller on the given 28 platform 29- qcom,data-crci: must contain the ADM data type CRCI block instance 30 number specified for the NAND controller on the given 31 platform 32 33QPIC specific properties: 34- dmas: DMA specifier, consisting of a phandle to the BAM DMA 35 and the channel number to be used for NAND. Refer to 36 dma.txt, qcom_bam_dma.txt for more details 37- dma-names: must contain all 3 channel names : "tx", "rx", "cmd" 38- #address-cells: <1> - subnodes give the chip-select number 39- #size-cells: <0> 40 41* NAND chip-select 42 43Each controller may contain one or more subnodes to represent enabled 44chip-selects which (may) contain NAND flash chips. Their properties are as 45follows. 46 47Required properties: 48- reg: a single integer representing the chip-select 49 number (e.g., 0, 1, 2, etc.) 50- #address-cells: see partition.txt 51- #size-cells: see partition.txt 52 53Optional properties: 54- nand-bus-width: see nand-controller.yaml 55- nand-ecc-strength: see nand-controller.yaml. If not specified, then ECC strength will 56 be used according to chip requirement and available 57 OOB size. 58 59Each nandcs device node may optionally contain a 'partitions' sub-node, which 60further contains sub-nodes describing the flash partition mapping. See 61partition.txt for more detail. 62 63Example: 64 65nand-controller@1ac00000 { 66 compatible = "qcom,ipq806x-nand"; 67 reg = <0x1ac00000 0x800>; 68 69 clocks = <&gcc EBI2_CLK>, 70 <&gcc EBI2_AON_CLK>; 71 clock-names = "core", "aon"; 72 73 dmas = <&adm_dma 3>; 74 dma-names = "rxtx"; 75 qcom,cmd-crci = <15>; 76 qcom,data-crci = <3>; 77 78 #address-cells = <1>; 79 #size-cells = <0>; 80 81 nand@0 { 82 reg = <0>; 83 84 nand-ecc-strength = <4>; 85 nand-bus-width = <8>; 86 87 partitions { 88 compatible = "fixed-partitions"; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 92 partition@0 { 93 label = "boot-nand"; 94 reg = <0 0x58a0000>; 95 }; 96 97 partition@58a0000 { 98 label = "fs-nand"; 99 reg = <0x58a0000 0x4000000>; 100 }; 101 }; 102 }; 103}; 104 105nand-controller@79b0000 { 106 compatible = "qcom,ipq4019-nand"; 107 reg = <0x79b0000 0x1000>; 108 109 clocks = <&gcc GCC_QPIC_CLK>, 110 <&gcc GCC_QPIC_AHB_CLK>; 111 clock-names = "core", "aon"; 112 113 dmas = <&qpicbam 0>, 114 <&qpicbam 1>, 115 <&qpicbam 2>; 116 dma-names = "tx", "rx", "cmd"; 117 118 #address-cells = <1>; 119 #size-cells = <0>; 120 121 nand@0 { 122 reg = <0>; 123 nand-ecc-strength = <4>; 124 nand-bus-width = <8>; 125 126 partitions { 127 compatible = "fixed-partitions"; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 131 partition@0 { 132 label = "boot-nand"; 133 reg = <0 0x58a0000>; 134 }; 135 136 partition@58a0000 { 137 label = "fs-nand"; 138 reg = <0x58a0000 0x4000000>; 139 }; 140 }; 141 }; 142}; 143