1MTK SoCs NAND FLASH controller (NFC) DT binding 2 3This file documents the device tree bindings for MTK SoCs NAND controllers. 4The functional split of the controller requires two drivers to operate: 5the nand controller interface driver and the ECC engine driver. 6 7The hardware description for both devices must be captured as device 8tree nodes. 9 101) NFC NAND Controller Interface (NFI): 11======================================= 12 13The first part of NFC is NAND Controller Interface (NFI) HW. 14Required NFI properties: 15- compatible: Should be one of 16 "mediatek,mt2701-nfc", 17 "mediatek,mt2712-nfc", 18 "mediatek,mt7622-nfc". 19- reg: Base physical address and size of NFI. 20- interrupts: Interrupts of NFI. 21- clocks: NFI required clocks. 22- clock-names: NFI clocks internal name. 23- ecc-engine: Required ECC Engine node. 24- #address-cells: NAND chip index, should be 1. 25- #size-cells: Should be 0. 26 27Example: 28 29 nandc: nfi@1100d000 { 30 compatible = "mediatek,mt2701-nfc"; 31 reg = <0 0x1100d000 0 0x1000>; 32 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>; 33 clocks = <&pericfg CLK_PERI_NFI>, 34 <&pericfg CLK_PERI_NFI_PAD>; 35 clock-names = "nfi_clk", "pad_clk"; 36 ecc-engine = <&bch>; 37 #address-cells = <1>; 38 #size-cells = <0>; 39 }; 40 41Platform related properties, should be set in {platform_name}.dts: 42- children nodes: NAND chips. 43 44Children nodes properties: 45- reg: Chip Select Signal, default 0. 46 Set as reg = <0>, <1> when need 2 CS. 47Optional: 48- nand-on-flash-bbt: Store BBT on NAND Flash. 49- nand-ecc-mode: the NAND ecc mode (check driver for supported modes) 50- nand-ecc-step-size: Number of data bytes covered by a single ECC step. 51 valid values: 52 512 and 1024 on mt2701 and mt2712. 53 512 only on mt7622. 54 1024 is recommended for large page NANDs. 55- nand-ecc-strength: Number of bits to correct per ECC step. 56 The valid values that each controller supports: 57 mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 58 32, 36, 40, 44, 48, 52, 56, 60. 59 mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 60 32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80. 61 mt7622: 4, 6, 8, 10, 12, 14, 16. 62 The strength should be calculated as follows: 63 E = (S - F) * 8 / B 64 S = O / (P / Q) 65 E : nand-ecc-strength. 66 S : spare size per sector. 67 F : FDM size, should be in the range [1,8]. 68 It is used to store free oob data. 69 O : oob size. 70 P : page size. 71 Q : nand-ecc-step-size. 72 B : number of parity bits needed to correct 73 1 bitflip. 74 According to MTK NAND controller design, 75 this number depends on max ecc step size 76 that MTK NAND controller supports. 77 If max ecc step size supported is 1024, 78 then it should be always 14. And if max 79 ecc step size is 512, then it should be 80 always 13. 81 If the result does not match any one of the listed 82 choices above, please select the smaller valid value from 83 the list. 84 (otherwise the driver will do the adjustment at runtime) 85- pinctrl-names: Default NAND pin GPIO setting name. 86- pinctrl-0: GPIO setting node. 87 88Example: 89 &pio { 90 nand_pins_default: nanddefault { 91 pins_dat { 92 pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>, 93 <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>, 94 <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>, 95 <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>, 96 <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>, 97 <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>, 98 <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>, 99 <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>, 100 <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>; 101 input-enable; 102 drive-strength = <MTK_DRIVE_8mA>; 103 bias-pull-up; 104 }; 105 106 pins_we { 107 pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>; 108 drive-strength = <MTK_DRIVE_8mA>; 109 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 110 }; 111 112 pins_ale { 113 pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>; 114 drive-strength = <MTK_DRIVE_8mA>; 115 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 116 }; 117 }; 118 }; 119 120 &nandc { 121 status = "okay"; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&nand_pins_default>; 124 nand@0 { 125 reg = <0>; 126 nand-on-flash-bbt; 127 nand-ecc-mode = "hw"; 128 nand-ecc-strength = <24>; 129 nand-ecc-step-size = <1024>; 130 }; 131 }; 132 133NAND chip optional subnodes: 134- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt 135 136Example: 137 nand@0 { 138 partitions { 139 compatible = "fixed-partitions"; 140 #address-cells = <1>; 141 #size-cells = <1>; 142 143 preloader@0 { 144 label = "pl"; 145 read-only; 146 reg = <0x00000000 0x00400000>; 147 }; 148 android@00400000 { 149 label = "android"; 150 reg = <0x00400000 0x12c00000>; 151 }; 152 }; 153 }; 154 1552) ECC Engine: 156============== 157 158Required BCH properties: 159- compatible: Should be one of 160 "mediatek,mt2701-ecc", 161 "mediatek,mt2712-ecc", 162 "mediatek,mt7622-ecc". 163- reg: Base physical address and size of ECC. 164- interrupts: Interrupts of ECC. 165- clocks: ECC required clocks. 166- clock-names: ECC clocks internal name. 167 168Example: 169 170 bch: ecc@1100e000 { 171 compatible = "mediatek,mt2701-ecc"; 172 reg = <0 0x1100e000 0 0x1000>; 173 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; 174 clocks = <&pericfg CLK_PERI_NFI_ECC>; 175 clock-names = "nfiecc_clk"; 176 }; 177