1CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...) 2 3Flash chips (Memory Technology Devices) are often used for solid state 4file systems on embedded devices. 5 6 - compatible : should contain the specific model of mtd chip(s) 7 used, if known, followed by either "cfi-flash", "jedec-flash", 8 "mtd-ram" or "mtd-rom". 9 - reg : Address range(s) of the mtd chip(s) 10 It's possible to (optionally) define multiple "reg" tuples so that 11 non-identical chips can be described in one node. 12 - bank-width : Width (in bytes) of the bank. Equal to the 13 device width times the number of interleaved chips. 14 - device-width : (optional) Width of a single mtd chip. If 15 omitted, assumed to be equal to 'bank-width'. 16 - #address-cells, #size-cells : Must be present if the device has 17 sub-nodes representing partitions (see below). In this case 18 both #address-cells and #size-cells must be equal to 1. 19 - no-unaligned-direct-access: boolean to disable the default direct 20 mapping of the flash. 21 On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause 22 problems with JFFS2 usage, as the local bus (LPB) doesn't support 23 unaligned accesses as implemented in the JFFS2 code via memcpy(). 24 By defining "no-unaligned-direct-access", the flash will not be 25 exposed directly to the MTD users (e.g. JFFS2) any more. 26 - linux,mtd-name: allow to specify the mtd name for retro capability with 27 physmap-flash drivers as boot loader pass the mtd partition via the old 28 device name physmap-flash. 29 - use-advanced-sector-protection: boolean to enable support for the 30 advanced sector protection (Spansion: PPB - Persistent Protection 31 Bits) locking. 32 - addr-gpios : (optional) List of GPIO descriptors that will be used to 33 address the MSBs address lines. The order goes from LSB to MSB. 34 35For JEDEC compatible devices, the following additional properties 36are defined: 37 38 - vendor-id : Contains the flash chip's vendor id (1 byte). 39 - device-id : Contains the flash chip's device id (1 byte). 40 41For ROM compatible devices (and ROM fallback from cfi-flash), the following 42additional (optional) property is defined: 43 44 - erase-size : The chip's physical erase block size in bytes. 45 46 The device tree may optionally contain endianness property. 47 little-endian or big-endian : It Represents the endianness that should be used 48 by the controller to properly read/write data 49 from/to the flash. If this property is missing, 50 the endianness is chosen by the system 51 (potentially based on extra configuration options). 52 53The device tree may optionally contain sub-nodes describing partitions of the 54address space. See partition.txt for more detail. 55 56Example: 57 58 flash@ff000000 { 59 compatible = "amd,am29lv128ml", "cfi-flash"; 60 reg = <ff000000 01000000>; 61 bank-width = <4>; 62 device-width = <1>; 63 #address-cells = <1>; 64 #size-cells = <1>; 65 fs@0 { 66 label = "fs"; 67 reg = <0 f80000>; 68 }; 69 firmware@f80000 { 70 label ="firmware"; 71 reg = <f80000 80000>; 72 read-only; 73 }; 74 }; 75 76Here an example with multiple "reg" tuples: 77 78 flash@f0000000,0 { 79 #address-cells = <1>; 80 #size-cells = <1>; 81 compatible = "intel,PC48F4400P0VB", "cfi-flash"; 82 reg = <0 0x00000000 0x02000000 83 0 0x02000000 0x02000000>; 84 bank-width = <2>; 85 partition@0 { 86 label = "test-part1"; 87 reg = <0 0x04000000>; 88 }; 89 }; 90 91An example using SRAM: 92 93 sram@2,0 { 94 compatible = "samsung,k6f1616u6a", "mtd-ram"; 95 reg = <2 0 0x00200000>; 96 bank-width = <2>; 97 }; 98 99An example using gpio-addrs 100 101 flash@20000000 { 102 #address-cells = <1>; 103 #size-cells = <1>; 104 compatible = "cfi-flash", "jedec-flash"; 105 reg = <0x20000000 0x02000000>; 106 ranges = <0 0x00000000 0x02000000 107 1 0x02000000 0x02000000>; 108 bank-width = <2>; 109 addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 110 partition@0 { 111 label = "test-part1"; 112 reg = <0 0x04000000>; 113 }; 114 }; 115