1NXP LPC32xx SoC NAND SLC controller 2 3Required properties: 4- compatible: "nxp,lpc3220-slc" 5- reg: Address and size of the controller 6- nand-on-flash-bbt: Use bad block table on flash 7- gpios: GPIO specification for NAND write protect 8 9The following required properties are very controller specific. See the LPC32xx 10User Manual: 11- nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY) 12- nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY) 13(The following values are specified in Hz, to make them independent of actual 14clock speed:) 15- nxp,wwidth: Write pulse width (W_WIDTH) 16- nxp,whold: Write hold time (W_HOLD) 17- nxp,wsetup: Write setup time (W_SETUP) 18- nxp,rwidth: Read pulse width (R_WIDTH) 19- nxp,rhold: Read hold time (R_HOLD) 20- nxp,rsetup: Read setup time (R_SETUP) 21 22Optional subnodes: 23- Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml 24 25Example: 26 27 slc: flash@20020000 { 28 compatible = "nxp,lpc3220-slc"; 29 reg = <0x20020000 0x1000>; 30 #address-cells = <1>; 31 #size-cells = <1>; 32 33 nxp,wdr-clks = <14>; 34 nxp,wwidth = <40000000>; 35 nxp,whold = <100000000>; 36 nxp,wsetup = <100000000>; 37 nxp,rdr-clks = <14>; 38 nxp,rwidth = <40000000>; 39 nxp,rhold = <66666666>; 40 nxp,rsetup = <100000000>; 41 nand-on-flash-bbt; 42 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ 43 44 mtd0@00000000 { 45 label = "phy3250-boot"; 46 reg = <0x00000000 0x00064000>; 47 read-only; 48 }; 49 50 ... 51 52 }; 53