xref: /freebsd/sys/contrib/device-tree/Bindings/mmc/sdhci-msm.yaml (revision e9ac41698b2f322d55ccf9da50a3596edb2c1800) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDHCI controller (sdhci-msm)
8
9maintainers:
10  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
11
12description:
13  Secure Digital Host Controller Interface (SDHCI) present on
14  Qualcomm SOCs supports SD/MMC/SDIO devices.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - qcom,sdhci-msm-v4
21        deprecated: true
22      - items:
23          - enum:
24              - qcom,apq8084-sdhci
25              - qcom,ipq4019-sdhci
26              - qcom,ipq8074-sdhci
27              - qcom,msm8226-sdhci
28              - qcom,msm8953-sdhci
29              - qcom,msm8974-sdhci
30              - qcom,msm8976-sdhci
31              - qcom,msm8916-sdhci
32              - qcom,msm8992-sdhci
33              - qcom,msm8994-sdhci
34              - qcom,msm8996-sdhci
35              - qcom,msm8998-sdhci
36          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
37      - items:
38          - enum:
39              - qcom,ipq5018-sdhci
40              - qcom,ipq5332-sdhci
41              - qcom,ipq6018-sdhci
42              - qcom,ipq9574-sdhci
43              - qcom,qcm2290-sdhci
44              - qcom,qcs404-sdhci
45              - qcom,qdu1000-sdhci
46              - qcom,sc7180-sdhci
47              - qcom,sc7280-sdhci
48              - qcom,sc8280xp-sdhci
49              - qcom,sdm630-sdhci
50              - qcom,sdm670-sdhci
51              - qcom,sdm845-sdhci
52              - qcom,sdx55-sdhci
53              - qcom,sdx65-sdhci
54              - qcom,sm6115-sdhci
55              - qcom,sm6125-sdhci
56              - qcom,sm6350-sdhci
57              - qcom,sm6375-sdhci
58              - qcom,sm8150-sdhci
59              - qcom,sm8250-sdhci
60              - qcom,sm8350-sdhci
61              - qcom,sm8450-sdhci
62              - qcom,sm8550-sdhci
63              - qcom,sm8650-sdhci
64          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
65
66  reg:
67    minItems: 1
68    maxItems: 4
69
70  reg-names:
71    minItems: 1
72    maxItems: 4
73
74  clocks:
75    minItems: 2
76    items:
77      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
78      - description: SDC MMC clock, MCLK
79      - description: TCXO clock
80      - description: clock for Inline Crypto Engine
81      - description: SDCC bus voter clock
82      - description: reference clock for RCLK delay calibration
83      - description: sleep clock for RCLK delay calibration
84
85  clock-names:
86    minItems: 2
87    items:
88      - const: iface
89      - const: core
90      - const: xo
91      - enum: [ice, bus, cal, sleep]
92      - enum: [ice, bus, cal, sleep]
93      - enum: [ice, bus, cal, sleep]
94      - enum: [ice, bus, cal, sleep]
95
96  dma-coherent: true
97
98  interrupts:
99    maxItems: 2
100
101  interrupt-names:
102    items:
103      - const: hc_irq
104      - const: pwr_irq
105
106  pinctrl-names:
107    minItems: 1
108    items:
109      - const: default
110      - const: sleep
111
112  pinctrl-0:
113    description:
114      Should specify pin control groups used for this controller.
115
116  pinctrl-1:
117    description:
118      Should specify sleep pin control groups used for this controller.
119
120  resets:
121    maxItems: 1
122
123  qcom,ddr-config:
124    $ref: /schemas/types.yaml#/definitions/uint32
125    description: platform specific settings for DDR_CONFIG reg.
126
127  qcom,dll-config:
128    $ref: /schemas/types.yaml#/definitions/uint32
129    description: platform specific settings for DLL_CONFIG reg.
130
131  iommus:
132    minItems: 1
133    maxItems: 8
134    description: |
135      phandle to apps_smmu node with sid mask.
136
137  interconnects:
138    minItems: 1
139    items:
140      - description: data path, sdhc to ddr
141      - description: config path, cpu to sdhc
142
143  interconnect-names:
144    minItems: 1
145    items:
146      - const: sdhc-ddr
147      - const: cpu-sdhc
148
149  power-domains:
150    description: A phandle to sdhci power domain node
151    maxItems: 1
152
153  operating-points-v2: true
154
155patternProperties:
156  '^opp-table(-[a-z0-9]+)?$':
157    if:
158      properties:
159        compatible:
160          const: operating-points-v2
161    then:
162      patternProperties:
163        '^opp-?[0-9]+$':
164          required:
165            - required-opps
166
167required:
168  - compatible
169  - reg
170  - clocks
171  - clock-names
172  - interrupts
173
174allOf:
175  - $ref: sdhci-common.yaml#
176
177  - if:
178      properties:
179        compatible:
180          contains:
181            enum:
182              - qcom,sdhci-msm-v4
183    then:
184      properties:
185        reg:
186          minItems: 2
187          items:
188            - description: Host controller register map
189            - description: SD Core register map
190            - description: CQE register map
191            - description: Inline Crypto Engine register map
192        reg-names:
193          minItems: 2
194          items:
195            - const: hc
196            - const: core
197            - const: cqhci
198            - const: ice
199    else:
200      properties:
201        reg:
202          minItems: 1
203          items:
204            - description: Host controller register map
205            - description: CQE register map
206            - description: Inline Crypto Engine register map
207        reg-names:
208          minItems: 1
209          items:
210            - const: hc
211            - const: cqhci
212            - const: ice
213
214unevaluatedProperties: false
215
216examples:
217  - |
218    #include <dt-bindings/interrupt-controller/arm-gic.h>
219    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
220    #include <dt-bindings/clock/qcom,rpmh.h>
221    #include <dt-bindings/power/qcom,rpmhpd.h>
222
223    sdhc_2: mmc@8804000 {
224      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
225      reg = <0 0x08804000 0 0x1000>;
226
227      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
228                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
229      interrupt-names = "hc_irq", "pwr_irq";
230
231      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
232               <&gcc GCC_SDCC2_APPS_CLK>,
233               <&rpmhcc RPMH_CXO_CLK>;
234      clock-names = "iface", "core", "xo";
235      iommus = <&apps_smmu 0x4a0 0x0>;
236      qcom,dll-config = <0x0007642c>;
237      qcom,ddr-config = <0x80040868>;
238      power-domains = <&rpmhpd RPMHPD_CX>;
239
240      operating-points-v2 = <&sdhc2_opp_table>;
241
242      sdhc2_opp_table: opp-table {
243        compatible = "operating-points-v2";
244
245        opp-19200000 {
246          opp-hz = /bits/ 64 <19200000>;
247          required-opps = <&rpmhpd_opp_min_svs>;
248        };
249
250        opp-50000000 {
251          opp-hz = /bits/ 64 <50000000>;
252          required-opps = <&rpmhpd_opp_low_svs>;
253        };
254
255        opp-100000000 {
256          opp-hz = /bits/ 64 <100000000>;
257          required-opps = <&rpmhpd_opp_svs>;
258        };
259
260        opp-202000000 {
261          opp-hz = /bits/ 64 <202000000>;
262          required-opps = <&rpmhpd_opp_svs_l1>;
263        };
264      };
265    };
266