xref: /freebsd/sys/contrib/device-tree/Bindings/mmc/sdhci-msm.yaml (revision b077aed33b7b6aefca7b17ddb250cf521f938613) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/mmc/sdhci-msm.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm SDHCI controller (sdhci-msm)
9
10maintainers:
11  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
12
13description:
14  Secure Digital Host Controller Interface (SDHCI) present on
15  Qualcomm SOCs supports SD/MMC/SDIO devices.
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - qcom,sdhci-msm-v4
22        deprecated: true
23      - items:
24          - enum:
25              - qcom,apq8084-sdhci
26              - qcom,msm8226-sdhci
27              - qcom,msm8953-sdhci
28              - qcom,msm8974-sdhci
29              - qcom,msm8916-sdhci
30              - qcom,msm8992-sdhci
31              - qcom,msm8994-sdhci
32              - qcom,msm8996-sdhci
33              - qcom,msm8998-sdhci
34          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
35      - items:
36          - enum:
37              - qcom,qcs404-sdhci
38              - qcom,sc7180-sdhci
39              - qcom,sc7280-sdhci
40              - qcom,sdm630-sdhci
41              - qcom,sdm845-sdhci
42              - qcom,sdx55-sdhci
43              - qcom,sdx65-sdhci
44              - qcom,sm6125-sdhci
45              - qcom,sm6350-sdhci
46              - qcom,sm8150-sdhci
47              - qcom,sm8250-sdhci
48              - qcom,sm8450-sdhci
49          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
50
51  reg:
52    minItems: 1
53    maxItems: 4
54
55  reg-names:
56    minItems: 1
57    maxItems: 4
58
59  clocks:
60    minItems: 3
61    items:
62      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
63      - description: SDC MMC clock, MCLK
64      - description: TCXO clock
65      - description: clock for Inline Crypto Engine
66      - description: SDCC bus voter clock
67      - description: reference clock for RCLK delay calibration
68      - description: sleep clock for RCLK delay calibration
69
70  clock-names:
71    minItems: 2
72    items:
73      - const: iface
74      - const: core
75      - const: xo
76      - const: ice
77      - const: bus
78      - const: cal
79      - const: sleep
80
81  interrupts:
82    maxItems: 2
83
84  interrupt-names:
85    items:
86      - const: hc_irq
87      - const: pwr_irq
88
89  pinctrl-names:
90    minItems: 1
91    items:
92      - const: default
93      - const: sleep
94
95  pinctrl-0:
96    description:
97      Should specify pin control groups used for this controller.
98
99  resets:
100    maxItems: 1
101
102  qcom,ddr-config:
103    $ref: /schemas/types.yaml#/definitions/uint32
104    description: platform specific settings for DDR_CONFIG reg.
105
106  qcom,dll-config:
107    $ref: /schemas/types.yaml#/definitions/uint32
108    description: platform specific settings for DLL_CONFIG reg.
109
110  iommus:
111    minItems: 1
112    maxItems: 8
113    description: |
114      phandle to apps_smmu node with sid mask.
115
116  interconnects:
117    items:
118      - description: data path, sdhc to ddr
119      - description: config path, cpu to sdhc
120
121  interconnect-names:
122    items:
123      - const: sdhc-ddr
124      - const: cpu-sdhc
125
126  power-domains:
127    description: A phandle to sdhci power domain node
128    maxItems: 1
129
130  mmc-ddr-1_8v: true
131
132  mmc-hs200-1_8v: true
133
134  mmc-hs400-1_8v: true
135
136  bus-width: true
137
138  max-frequency: true
139
140  operating-points-v2: true
141
142patternProperties:
143  '^opp-table(-[a-z0-9]+)?$':
144    if:
145      properties:
146        compatible:
147          const: operating-points-v2
148    then:
149      patternProperties:
150        '^opp-?[0-9]+$':
151          required:
152            - required-opps
153
154required:
155  - compatible
156  - reg
157  - clocks
158  - clock-names
159  - interrupts
160
161allOf:
162  - $ref: mmc-controller.yaml#
163
164  - if:
165      properties:
166        compatible:
167          contains:
168            enum:
169              - qcom,sdhci-msm-v4
170    then:
171      properties:
172        reg:
173          minItems: 2
174          items:
175            - description: Host controller register map
176            - description: SD Core register map
177            - description: CQE register map
178            - description: Inline Crypto Engine register map
179        reg-names:
180          minItems: 2
181          items:
182            - const: hc
183            - const: core
184            - const: cqhci
185            - const: ice
186    else:
187      properties:
188        reg:
189          minItems: 1
190          items:
191            - description: Host controller register map
192            - description: CQE register map
193            - description: Inline Crypto Engine register map
194        reg-names:
195          minItems: 1
196          items:
197            - const: hc
198            - const: cqhci
199            - const: ice
200
201unevaluatedProperties: false
202
203examples:
204  - |
205    #include <dt-bindings/interrupt-controller/arm-gic.h>
206    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
207    #include <dt-bindings/clock/qcom,rpmh.h>
208    #include <dt-bindings/power/qcom-rpmpd.h>
209
210    sdhc_2: mmc@8804000 {
211      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
212      reg = <0 0x08804000 0 0x1000>;
213
214      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
215                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
216      interrupt-names = "hc_irq", "pwr_irq";
217
218      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
219               <&gcc GCC_SDCC2_APPS_CLK>,
220               <&rpmhcc RPMH_CXO_CLK>;
221      clock-names = "iface", "core", "xo";
222      iommus = <&apps_smmu 0x4a0 0x0>;
223      qcom,dll-config = <0x0007642c>;
224      qcom,ddr-config = <0x80040868>;
225      power-domains = <&rpmhpd SM8250_CX>;
226
227      operating-points-v2 = <&sdhc2_opp_table>;
228
229      sdhc2_opp_table: opp-table {
230        compatible = "operating-points-v2";
231
232        opp-19200000 {
233          opp-hz = /bits/ 64 <19200000>;
234          required-opps = <&rpmhpd_opp_min_svs>;
235        };
236
237        opp-50000000 {
238          opp-hz = /bits/ 64 <50000000>;
239          required-opps = <&rpmhpd_opp_low_svs>;
240        };
241
242        opp-100000000 {
243          opp-hz = /bits/ 64 <100000000>;
244          required-opps = <&rpmhpd_opp_svs>;
245        };
246
247        opp-202000000 {
248          opp-hz = /bits/ 64 <202000000>;
249          required-opps = <&rpmhpd_opp_svs_l1>;
250        };
251      };
252    };
253