1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SDHCI controller (sdhci-msm) 8 9maintainers: 10 - Bhupesh Sharma <bhupesh.sharma@linaro.org> 11 12description: 13 Secure Digital Host Controller Interface (SDHCI) present on 14 Qualcomm SOCs supports SD/MMC/SDIO devices. 15 16properties: 17 compatible: 18 oneOf: 19 - enum: 20 - qcom,sdhci-msm-v4 21 deprecated: true 22 - items: 23 - enum: 24 - qcom,apq8084-sdhci 25 - qcom,msm8226-sdhci 26 - qcom,msm8953-sdhci 27 - qcom,msm8974-sdhci 28 - qcom,msm8976-sdhci 29 - qcom,msm8916-sdhci 30 - qcom,msm8992-sdhci 31 - qcom,msm8994-sdhci 32 - qcom,msm8996-sdhci 33 - qcom,msm8998-sdhci 34 - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0 35 - items: 36 - enum: 37 - qcom,ipq5018-sdhci 38 - qcom,ipq5332-sdhci 39 - qcom,ipq6018-sdhci 40 - qcom,ipq9574-sdhci 41 - qcom,qcm2290-sdhci 42 - qcom,qcs404-sdhci 43 - qcom,qdu1000-sdhci 44 - qcom,sc7180-sdhci 45 - qcom,sc7280-sdhci 46 - qcom,sc8280xp-sdhci 47 - qcom,sdm630-sdhci 48 - qcom,sdm670-sdhci 49 - qcom,sdm845-sdhci 50 - qcom,sdx55-sdhci 51 - qcom,sdx65-sdhci 52 - qcom,sm6115-sdhci 53 - qcom,sm6125-sdhci 54 - qcom,sm6350-sdhci 55 - qcom,sm6375-sdhci 56 - qcom,sm8150-sdhci 57 - qcom,sm8250-sdhci 58 - qcom,sm8350-sdhci 59 - qcom,sm8450-sdhci 60 - qcom,sm8550-sdhci 61 - const: qcom,sdhci-msm-v5 # for sdcc version 5.0 62 63 reg: 64 minItems: 1 65 maxItems: 4 66 67 reg-names: 68 minItems: 1 69 maxItems: 4 70 71 clocks: 72 minItems: 3 73 items: 74 - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock 75 - description: SDC MMC clock, MCLK 76 - description: TCXO clock 77 - description: clock for Inline Crypto Engine 78 - description: SDCC bus voter clock 79 - description: reference clock for RCLK delay calibration 80 - description: sleep clock for RCLK delay calibration 81 82 clock-names: 83 minItems: 2 84 items: 85 - const: iface 86 - const: core 87 - const: xo 88 - const: ice 89 - const: bus 90 - const: cal 91 - const: sleep 92 93 dma-coherent: true 94 95 interrupts: 96 maxItems: 2 97 98 interrupt-names: 99 items: 100 - const: hc_irq 101 - const: pwr_irq 102 103 pinctrl-names: 104 minItems: 1 105 items: 106 - const: default 107 - const: sleep 108 109 pinctrl-0: 110 description: 111 Should specify pin control groups used for this controller. 112 113 pinctrl-1: 114 description: 115 Should specify sleep pin control groups used for this controller. 116 117 resets: 118 maxItems: 1 119 120 qcom,ddr-config: 121 $ref: /schemas/types.yaml#/definitions/uint32 122 description: platform specific settings for DDR_CONFIG reg. 123 124 qcom,dll-config: 125 $ref: /schemas/types.yaml#/definitions/uint32 126 description: platform specific settings for DLL_CONFIG reg. 127 128 iommus: 129 minItems: 1 130 maxItems: 8 131 description: | 132 phandle to apps_smmu node with sid mask. 133 134 interconnects: 135 minItems: 1 136 items: 137 - description: data path, sdhc to ddr 138 - description: config path, cpu to sdhc 139 140 interconnect-names: 141 minItems: 1 142 items: 143 - const: sdhc-ddr 144 - const: cpu-sdhc 145 146 power-domains: 147 description: A phandle to sdhci power domain node 148 maxItems: 1 149 150 operating-points-v2: true 151 152patternProperties: 153 '^opp-table(-[a-z0-9]+)?$': 154 if: 155 properties: 156 compatible: 157 const: operating-points-v2 158 then: 159 patternProperties: 160 '^opp-?[0-9]+$': 161 required: 162 - required-opps 163 164required: 165 - compatible 166 - reg 167 - clocks 168 - clock-names 169 - interrupts 170 171allOf: 172 - $ref: sdhci-common.yaml# 173 174 - if: 175 properties: 176 compatible: 177 contains: 178 enum: 179 - qcom,sdhci-msm-v4 180 then: 181 properties: 182 reg: 183 minItems: 2 184 items: 185 - description: Host controller register map 186 - description: SD Core register map 187 - description: CQE register map 188 - description: Inline Crypto Engine register map 189 reg-names: 190 minItems: 2 191 items: 192 - const: hc 193 - const: core 194 - const: cqhci 195 - const: ice 196 else: 197 properties: 198 reg: 199 minItems: 1 200 items: 201 - description: Host controller register map 202 - description: CQE register map 203 - description: Inline Crypto Engine register map 204 reg-names: 205 minItems: 1 206 items: 207 - const: hc 208 - const: cqhci 209 - const: ice 210 211unevaluatedProperties: false 212 213examples: 214 - | 215 #include <dt-bindings/interrupt-controller/arm-gic.h> 216 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 217 #include <dt-bindings/clock/qcom,rpmh.h> 218 #include <dt-bindings/power/qcom-rpmpd.h> 219 220 sdhc_2: mmc@8804000 { 221 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 222 reg = <0 0x08804000 0 0x1000>; 223 224 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 226 interrupt-names = "hc_irq", "pwr_irq"; 227 228 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 229 <&gcc GCC_SDCC2_APPS_CLK>, 230 <&rpmhcc RPMH_CXO_CLK>; 231 clock-names = "iface", "core", "xo"; 232 iommus = <&apps_smmu 0x4a0 0x0>; 233 qcom,dll-config = <0x0007642c>; 234 qcom,ddr-config = <0x80040868>; 235 power-domains = <&rpmhpd SM8250_CX>; 236 237 operating-points-v2 = <&sdhc2_opp_table>; 238 239 sdhc2_opp_table: opp-table { 240 compatible = "operating-points-v2"; 241 242 opp-19200000 { 243 opp-hz = /bits/ 64 <19200000>; 244 required-opps = <&rpmhpd_opp_min_svs>; 245 }; 246 247 opp-50000000 { 248 opp-hz = /bits/ 64 <50000000>; 249 required-opps = <&rpmhpd_opp_low_svs>; 250 }; 251 252 opp-100000000 { 253 opp-hz = /bits/ 64 <100000000>; 254 required-opps = <&rpmhpd_opp_svs>; 255 }; 256 257 opp-202000000 { 258 opp-hz = /bits/ 64 <202000000>; 259 required-opps = <&rpmhpd_opp_svs_l1>; 260 }; 261 }; 262 }; 263