xref: /freebsd/sys/contrib/device-tree/Bindings/mmc/sdhci-msm.yaml (revision 2e3f49888ec8851bafb22011533217487764fdb0) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDHCI controller (sdhci-msm)
8
9maintainers:
10  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
11
12description:
13  Secure Digital Host Controller Interface (SDHCI) present on
14  Qualcomm SOCs supports SD/MMC/SDIO devices.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - qcom,sdhci-msm-v4
21        deprecated: true
22      - items:
23          - enum:
24              - qcom,apq8084-sdhci
25              - qcom,msm8226-sdhci
26              - qcom,msm8953-sdhci
27              - qcom,msm8974-sdhci
28              - qcom,msm8976-sdhci
29              - qcom,msm8916-sdhci
30              - qcom,msm8992-sdhci
31              - qcom,msm8994-sdhci
32              - qcom,msm8996-sdhci
33              - qcom,msm8998-sdhci
34          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
35      - items:
36          - enum:
37              - qcom,ipq5018-sdhci
38              - qcom,ipq5332-sdhci
39              - qcom,ipq9574-sdhci
40              - qcom,qcm2290-sdhci
41              - qcom,qcs404-sdhci
42              - qcom,sc7180-sdhci
43              - qcom,sc7280-sdhci
44              - qcom,sdm630-sdhci
45              - qcom,sdm670-sdhci
46              - qcom,sdm845-sdhci
47              - qcom,sdx55-sdhci
48              - qcom,sdx65-sdhci
49              - qcom,sm6115-sdhci
50              - qcom,sm6125-sdhci
51              - qcom,sm6350-sdhci
52              - qcom,sm6375-sdhci
53              - qcom,sm8150-sdhci
54              - qcom,sm8250-sdhci
55              - qcom,sm8350-sdhci
56              - qcom,sm8450-sdhci
57              - qcom,sm8550-sdhci
58          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
59
60  reg:
61    minItems: 1
62    maxItems: 4
63
64  reg-names:
65    minItems: 1
66    maxItems: 4
67
68  clocks:
69    minItems: 3
70    items:
71      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
72      - description: SDC MMC clock, MCLK
73      - description: TCXO clock
74      - description: clock for Inline Crypto Engine
75      - description: SDCC bus voter clock
76      - description: reference clock for RCLK delay calibration
77      - description: sleep clock for RCLK delay calibration
78
79  clock-names:
80    minItems: 2
81    items:
82      - const: iface
83      - const: core
84      - const: xo
85      - const: ice
86      - const: bus
87      - const: cal
88      - const: sleep
89
90  dma-coherent: true
91
92  interrupts:
93    maxItems: 2
94
95  interrupt-names:
96    items:
97      - const: hc_irq
98      - const: pwr_irq
99
100  pinctrl-names:
101    minItems: 1
102    items:
103      - const: default
104      - const: sleep
105
106  pinctrl-0:
107    description:
108      Should specify pin control groups used for this controller.
109
110  pinctrl-1:
111    description:
112      Should specify sleep pin control groups used for this controller.
113
114  resets:
115    maxItems: 1
116
117  qcom,ddr-config:
118    $ref: /schemas/types.yaml#/definitions/uint32
119    description: platform specific settings for DDR_CONFIG reg.
120
121  qcom,dll-config:
122    $ref: /schemas/types.yaml#/definitions/uint32
123    description: platform specific settings for DLL_CONFIG reg.
124
125  iommus:
126    minItems: 1
127    maxItems: 8
128    description: |
129      phandle to apps_smmu node with sid mask.
130
131  interconnects:
132    minItems: 1
133    items:
134      - description: data path, sdhc to ddr
135      - description: config path, cpu to sdhc
136
137  interconnect-names:
138    minItems: 1
139    items:
140      - const: sdhc-ddr
141      - const: cpu-sdhc
142
143  power-domains:
144    description: A phandle to sdhci power domain node
145    maxItems: 1
146
147  operating-points-v2: true
148
149patternProperties:
150  '^opp-table(-[a-z0-9]+)?$':
151    if:
152      properties:
153        compatible:
154          const: operating-points-v2
155    then:
156      patternProperties:
157        '^opp-?[0-9]+$':
158          required:
159            - required-opps
160
161required:
162  - compatible
163  - reg
164  - clocks
165  - clock-names
166  - interrupts
167
168allOf:
169  - $ref: sdhci-common.yaml#
170
171  - if:
172      properties:
173        compatible:
174          contains:
175            enum:
176              - qcom,sdhci-msm-v4
177    then:
178      properties:
179        reg:
180          minItems: 2
181          items:
182            - description: Host controller register map
183            - description: SD Core register map
184            - description: CQE register map
185            - description: Inline Crypto Engine register map
186        reg-names:
187          minItems: 2
188          items:
189            - const: hc
190            - const: core
191            - const: cqhci
192            - const: ice
193    else:
194      properties:
195        reg:
196          minItems: 1
197          items:
198            - description: Host controller register map
199            - description: CQE register map
200            - description: Inline Crypto Engine register map
201        reg-names:
202          minItems: 1
203          items:
204            - const: hc
205            - const: cqhci
206            - const: ice
207
208unevaluatedProperties: false
209
210examples:
211  - |
212    #include <dt-bindings/interrupt-controller/arm-gic.h>
213    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
214    #include <dt-bindings/clock/qcom,rpmh.h>
215    #include <dt-bindings/power/qcom-rpmpd.h>
216
217    sdhc_2: mmc@8804000 {
218      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
219      reg = <0 0x08804000 0 0x1000>;
220
221      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
222                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
223      interrupt-names = "hc_irq", "pwr_irq";
224
225      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
226               <&gcc GCC_SDCC2_APPS_CLK>,
227               <&rpmhcc RPMH_CXO_CLK>;
228      clock-names = "iface", "core", "xo";
229      iommus = <&apps_smmu 0x4a0 0x0>;
230      qcom,dll-config = <0x0007642c>;
231      qcom,ddr-config = <0x80040868>;
232      power-domains = <&rpmhpd SM8250_CX>;
233
234      operating-points-v2 = <&sdhc2_opp_table>;
235
236      sdhc2_opp_table: opp-table {
237        compatible = "operating-points-v2";
238
239        opp-19200000 {
240          opp-hz = /bits/ 64 <19200000>;
241          required-opps = <&rpmhpd_opp_min_svs>;
242        };
243
244        opp-50000000 {
245          opp-hz = /bits/ 64 <50000000>;
246          required-opps = <&rpmhpd_opp_low_svs>;
247        };
248
249        opp-100000000 {
250          opp-hz = /bits/ 64 <100000000>;
251          required-opps = <&rpmhpd_opp_svs>;
252        };
253
254        opp-202000000 {
255          opp-hz = /bits/ 64 <202000000>;
256          required-opps = <&rpmhpd_opp_svs_l1>;
257        };
258      };
259    };
260