xref: /freebsd/sys/contrib/device-tree/Bindings/mmc/sdhci-am654.yaml (revision e6bfd18d21b225af6a0ed67ceeaf1293b7b9eba5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: TI AM654 MMC Controller
9
10maintainers:
11  - Ulf Hansson <ulf.hansson@linaro.org>
12
13allOf:
14  - $ref: mmc-controller.yaml#
15
16properties:
17  compatible:
18    oneOf:
19      - const: ti,am654-sdhci-5.1
20      - const: ti,j721e-sdhci-8bit
21      - const: ti,j721e-sdhci-4bit
22      - const: ti,am64-sdhci-8bit
23      - const: ti,am64-sdhci-4bit
24      - const: ti,am62-sdhci
25      - items:
26          - const: ti,j7200-sdhci-8bit
27          - const: ti,j721e-sdhci-8bit
28      - items:
29          - const: ti,j7200-sdhci-4bit
30          - const: ti,j721e-sdhci-4bit
31
32  reg:
33    maxItems: 2
34
35  interrupts:
36    maxItems: 1
37
38  power-domains:
39    maxItems: 1
40
41  clocks:
42    minItems: 1
43    maxItems: 2
44    description: Handles to input clocks
45
46  clock-names:
47    minItems: 1
48    items:
49      - const: clk_ahb
50      - const: clk_xin
51
52  sdhci-caps-mask: true
53
54  # PHY output tap delays:
55  # Used to delay the data valid window and align it to the sampling clock.
56  # Binding needs to be provided for each supported speed mode otherwise the
57  # corresponding mode will be disabled.
58
59  ti,otap-del-sel-legacy:
60    description: Output tap delay for SD/MMC legacy timing
61    $ref: "/schemas/types.yaml#/definitions/uint32"
62    minimum: 0
63    maximum: 0xf
64
65  ti,otap-del-sel-mmc-hs:
66    description: Output tap delay for MMC high speed timing
67    $ref: "/schemas/types.yaml#/definitions/uint32"
68    minimum: 0
69    maximum: 0xf
70
71  ti,otap-del-sel-sd-hs:
72    description: Output tap delay for SD high speed timing
73    $ref: "/schemas/types.yaml#/definitions/uint32"
74    minimum: 0
75    maximum: 0xf
76
77  ti,otap-del-sel-sdr12:
78    description: Output tap delay for SD UHS SDR12 timing
79    $ref: "/schemas/types.yaml#/definitions/uint32"
80    minimum: 0
81    maximum: 0xf
82
83  ti,otap-del-sel-sdr25:
84    description: Output tap delay for SD UHS SDR25 timing
85    $ref: "/schemas/types.yaml#/definitions/uint32"
86    minimum: 0
87    maximum: 0xf
88
89  ti,otap-del-sel-sdr50:
90    description: Output tap delay for SD UHS SDR50 timing
91    $ref: "/schemas/types.yaml#/definitions/uint32"
92    minimum: 0
93    maximum: 0xf
94
95  ti,otap-del-sel-sdr104:
96    description: Output tap delay for SD UHS SDR104 timing
97    $ref: "/schemas/types.yaml#/definitions/uint32"
98    minimum: 0
99    maximum: 0xf
100
101  ti,otap-del-sel-ddr50:
102    description: Output tap delay for SD UHS DDR50 timing
103    $ref: "/schemas/types.yaml#/definitions/uint32"
104    minimum: 0
105    maximum: 0xf
106
107  ti,otap-del-sel-ddr52:
108    description: Output tap delay for eMMC DDR52 timing
109    $ref: "/schemas/types.yaml#/definitions/uint32"
110    minimum: 0
111    maximum: 0xf
112
113  ti,otap-del-sel-hs200:
114    description: Output tap delay for eMMC HS200 timing
115    $ref: "/schemas/types.yaml#/definitions/uint32"
116    minimum: 0
117    maximum: 0xf
118
119  ti,otap-del-sel-hs400:
120    description: Output tap delay for eMMC HS400 timing
121    $ref: "/schemas/types.yaml#/definitions/uint32"
122    minimum: 0
123    maximum: 0xf
124
125  # PHY input tap delays:
126  # Used to delay the data valid window and align it to the sampling clock for
127  # modes that don't support tuning
128
129  ti,itap-del-sel-legacy:
130    description: Input tap delay for SD/MMC legacy timing
131    $ref: "/schemas/types.yaml#/definitions/uint32"
132    minimum: 0
133    maximum: 0x1f
134
135  ti,itap-del-sel-mmc-hs:
136    description: Input tap delay for MMC high speed timing
137    $ref: "/schemas/types.yaml#/definitions/uint32"
138    minimum: 0
139    maximum: 0x1f
140
141  ti,itap-del-sel-sd-hs:
142    description: Input tap delay for SD high speed timing
143    $ref: "/schemas/types.yaml#/definitions/uint32"
144    minimum: 0
145    maximum: 0x1f
146
147  ti,itap-del-sel-sdr12:
148    description: Input tap delay for SD UHS SDR12 timing
149    $ref: "/schemas/types.yaml#/definitions/uint32"
150    minimum: 0
151    maximum: 0x1f
152
153  ti,itap-del-sel-sdr25:
154    description: Input tap delay for SD UHS SDR25 timing
155    $ref: "/schemas/types.yaml#/definitions/uint32"
156    minimum: 0
157    maximum: 0x1f
158
159  ti,itap-del-sel-ddr52:
160    description: Input tap delay for MMC DDR52 timing
161    $ref: "/schemas/types.yaml#/definitions/uint32"
162    minimum: 0
163    maximum: 0x1f
164
165  ti,trm-icp:
166    description: DLL trim select
167    $ref: "/schemas/types.yaml#/definitions/uint32"
168    minimum: 0
169    maximum: 0xf
170
171  ti,driver-strength-ohm:
172    description: DLL drive strength in ohms
173    $ref: "/schemas/types.yaml#/definitions/uint32"
174    enum:
175      - 33
176      - 40
177      - 50
178      - 66
179      - 100
180
181  ti,strobe-sel:
182    description: strobe select delay for HS400 speed mode.
183    $ref: "/schemas/types.yaml#/definitions/uint32"
184
185  ti,clkbuf-sel:
186    description: Clock Delay Buffer Select
187    $ref: "/schemas/types.yaml#/definitions/uint32"
188
189  ti,fails-without-test-cd:
190    $ref: /schemas/types.yaml#/definitions/flag
191    description:
192      When present, indicates that the CD line is not connected
193      and the controller is required to be forced into Test mode
194      to set the TESTCD bit.
195
196required:
197  - compatible
198  - reg
199  - interrupts
200  - clocks
201  - clock-names
202  - ti,otap-del-sel-legacy
203
204unevaluatedProperties: false
205
206examples:
207  - |
208    #include <dt-bindings/interrupt-controller/irq.h>
209    #include <dt-bindings/interrupt-controller/arm-gic.h>
210
211    bus {
212        #address-cells = <2>;
213        #size-cells = <2>;
214
215        mmc0: mmc@4f80000 {
216            compatible = "ti,am654-sdhci-5.1";
217            reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
218            power-domains = <&k3_pds 47>;
219            clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
220            clock-names = "clk_ahb", "clk_xin";
221            interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
222            sdhci-caps-mask = <0x80000007 0x0>;
223            mmc-ddr-1_8v;
224            ti,otap-del-sel-legacy = <0x0>;
225            ti,otap-del-sel-mmc-hs = <0x0>;
226            ti,otap-del-sel-ddr52 = <0x5>;
227            ti,otap-del-sel-hs200 = <0x5>;
228            ti,otap-del-sel-hs400 = <0x0>;
229            ti,itap-del-sel-legacy = <0x10>;
230            ti,itap-del-sel-mmc-hs = <0xa>;
231            ti,itap-del-sel-ddr52 = <0x3>;
232            ti,trm-icp = <0x8>;
233        };
234    };
235