1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: TI AM654 MMC Controller 9 10maintainers: 11 - Ulf Hansson <ulf.hansson@linaro.org> 12 13allOf: 14 - $ref: sdhci-common.yaml# 15 16properties: 17 compatible: 18 oneOf: 19 - enum: 20 - ti,am62-sdhci 21 - ti,am64-sdhci-4bit 22 - ti,am64-sdhci-8bit 23 - ti,am654-sdhci-5.1 24 - ti,j721e-sdhci-4bit 25 - ti,j721e-sdhci-8bit 26 - items: 27 - const: ti,j7200-sdhci-8bit 28 - const: ti,j721e-sdhci-8bit 29 - items: 30 - const: ti,j7200-sdhci-4bit 31 - const: ti,j721e-sdhci-4bit 32 33 reg: 34 maxItems: 2 35 36 interrupts: 37 maxItems: 1 38 39 power-domains: 40 maxItems: 1 41 42 clocks: 43 minItems: 1 44 maxItems: 2 45 description: Handles to input clocks 46 47 clock-names: 48 minItems: 1 49 items: 50 - const: clk_ahb 51 - const: clk_xin 52 53 dma-coherent: 54 type: boolean 55 56 # PHY output tap delays: 57 # Used to delay the data valid window and align it to the sampling clock. 58 # Binding needs to be provided for each supported speed mode otherwise the 59 # corresponding mode will be disabled. 60 61 ti,otap-del-sel-legacy: 62 description: Output tap delay for SD/MMC legacy timing 63 $ref: /schemas/types.yaml#/definitions/uint32 64 minimum: 0 65 maximum: 0xf 66 67 ti,otap-del-sel-mmc-hs: 68 description: Output tap delay for MMC high speed timing 69 $ref: /schemas/types.yaml#/definitions/uint32 70 minimum: 0 71 maximum: 0xf 72 73 ti,otap-del-sel-sd-hs: 74 description: Output tap delay for SD high speed timing 75 $ref: /schemas/types.yaml#/definitions/uint32 76 minimum: 0 77 maximum: 0xf 78 79 ti,otap-del-sel-sdr12: 80 description: Output tap delay for SD UHS SDR12 timing 81 $ref: /schemas/types.yaml#/definitions/uint32 82 minimum: 0 83 maximum: 0xf 84 85 ti,otap-del-sel-sdr25: 86 description: Output tap delay for SD UHS SDR25 timing 87 $ref: /schemas/types.yaml#/definitions/uint32 88 minimum: 0 89 maximum: 0xf 90 91 ti,otap-del-sel-sdr50: 92 description: Output tap delay for SD UHS SDR50 timing 93 $ref: /schemas/types.yaml#/definitions/uint32 94 minimum: 0 95 maximum: 0xf 96 97 ti,otap-del-sel-sdr104: 98 description: Output tap delay for SD UHS SDR104 timing 99 $ref: /schemas/types.yaml#/definitions/uint32 100 minimum: 0 101 maximum: 0xf 102 103 ti,otap-del-sel-ddr50: 104 description: Output tap delay for SD UHS DDR50 timing 105 $ref: /schemas/types.yaml#/definitions/uint32 106 minimum: 0 107 maximum: 0xf 108 109 ti,otap-del-sel-ddr52: 110 description: Output tap delay for eMMC DDR52 timing 111 $ref: /schemas/types.yaml#/definitions/uint32 112 minimum: 0 113 maximum: 0xf 114 115 ti,otap-del-sel-hs200: 116 description: Output tap delay for eMMC HS200 timing 117 $ref: /schemas/types.yaml#/definitions/uint32 118 minimum: 0 119 maximum: 0xf 120 121 ti,otap-del-sel-hs400: 122 description: Output tap delay for eMMC HS400 timing 123 $ref: /schemas/types.yaml#/definitions/uint32 124 minimum: 0 125 maximum: 0xf 126 127 # PHY input tap delays: 128 # Used to delay the data valid window and align it to the sampling clock for 129 # modes that don't support tuning 130 131 ti,itap-del-sel-legacy: 132 description: Input tap delay for SD/MMC legacy timing 133 $ref: /schemas/types.yaml#/definitions/uint32 134 minimum: 0 135 maximum: 0x1f 136 137 ti,itap-del-sel-mmc-hs: 138 description: Input tap delay for MMC high speed timing 139 $ref: /schemas/types.yaml#/definitions/uint32 140 minimum: 0 141 maximum: 0x1f 142 143 ti,itap-del-sel-sd-hs: 144 description: Input tap delay for SD high speed timing 145 $ref: /schemas/types.yaml#/definitions/uint32 146 minimum: 0 147 maximum: 0x1f 148 149 ti,itap-del-sel-sdr12: 150 description: Input tap delay for SD UHS SDR12 timing 151 $ref: /schemas/types.yaml#/definitions/uint32 152 minimum: 0 153 maximum: 0x1f 154 155 ti,itap-del-sel-sdr25: 156 description: Input tap delay for SD UHS SDR25 timing 157 $ref: /schemas/types.yaml#/definitions/uint32 158 minimum: 0 159 maximum: 0x1f 160 161 ti,itap-del-sel-ddr50: 162 description: Input tap delay for MMC DDR50 timing 163 $ref: /schemas/types.yaml#/definitions/uint32 164 minimum: 0 165 maximum: 0x1f 166 167 ti,itap-del-sel-ddr52: 168 description: Input tap delay for MMC DDR52 timing 169 $ref: /schemas/types.yaml#/definitions/uint32 170 minimum: 0 171 maximum: 0x1f 172 173 ti,trm-icp: 174 description: DLL trim select 175 $ref: /schemas/types.yaml#/definitions/uint32 176 minimum: 0 177 maximum: 0xf 178 179 ti,driver-strength-ohm: 180 description: DLL drive strength in ohms 181 $ref: /schemas/types.yaml#/definitions/uint32 182 enum: 183 - 33 184 - 40 185 - 50 186 - 66 187 - 100 188 189 ti,strobe-sel: 190 description: strobe select delay for HS400 speed mode. 191 $ref: /schemas/types.yaml#/definitions/uint32 192 193 ti,clkbuf-sel: 194 description: Clock Delay Buffer Select 195 $ref: /schemas/types.yaml#/definitions/uint32 196 197 ti,fails-without-test-cd: 198 $ref: /schemas/types.yaml#/definitions/flag 199 description: 200 When present, indicates that the CD line is not connected 201 and the controller is required to be forced into Test mode 202 to set the TESTCD bit. 203 204required: 205 - compatible 206 - reg 207 - interrupts 208 - clocks 209 - clock-names 210 - ti,otap-del-sel-legacy 211 212unevaluatedProperties: false 213 214examples: 215 - | 216 #include <dt-bindings/interrupt-controller/irq.h> 217 #include <dt-bindings/interrupt-controller/arm-gic.h> 218 219 bus { 220 #address-cells = <2>; 221 #size-cells = <2>; 222 223 mmc0: mmc@4f80000 { 224 compatible = "ti,am654-sdhci-5.1"; 225 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; 226 power-domains = <&k3_pds 47>; 227 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; 228 clock-names = "clk_ahb", "clk_xin"; 229 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 230 sdhci-caps-mask = <0x80000007 0x0>; 231 mmc-ddr-1_8v; 232 ti,otap-del-sel-legacy = <0x0>; 233 ti,otap-del-sel-mmc-hs = <0x0>; 234 ti,otap-del-sel-ddr52 = <0x5>; 235 ti,otap-del-sel-hs200 = <0x5>; 236 ti,otap-del-sel-hs400 = <0x0>; 237 ti,itap-del-sel-legacy = <0x10>; 238 ti,itap-del-sel-mmc-hs = <0xa>; 239 ti,itap-del-sel-ddr52 = <0x3>; 240 ti,trm-icp = <0x8>; 241 }; 242 }; 243