1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra Secure Digital Host Controller 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13description: | 14 This controller on Tegra family SoCs provides an interface for MMC, SD, and 15 SDIO types of memory cards. 16 17 This file documents differences between the core properties described by 18 mmc-controller.yaml and the properties for the Tegra SDHCI controller. 19 20properties: 21 compatible: 22 oneOf: 23 - enum: 24 - nvidia,tegra20-sdhci 25 - nvidia,tegra30-sdhci 26 - nvidia,tegra114-sdhci 27 - nvidia,tegra124-sdhci 28 - nvidia,tegra210-sdhci 29 - nvidia,tegra186-sdhci 30 - nvidia,tegra194-sdhci 31 32 - items: 33 - const: nvidia,tegra132-sdhci 34 - const: nvidia,tegra124-sdhci 35 36 - items: 37 - enum: 38 - nvidia,tegra194-sdhci 39 - nvidia,tegra234-sdhci 40 - const: nvidia,tegra186-sdhci 41 42 reg: 43 maxItems: 1 44 45 interrupts: 46 maxItems: 1 47 48 assigned-clocks: true 49 assigned-clock-parents: true 50 assigned-clock-rates: true 51 52 clocks: 53 minItems: 1 54 maxItems: 2 55 56 clock-names: 57 minItems: 1 58 maxItems: 2 59 60 resets: 61 items: 62 - description: module reset 63 64 reset-names: 65 items: 66 - const: sdhci 67 68 power-gpios: 69 description: specify GPIOs for power control 70 maxItems: 1 71 72 interconnects: 73 items: 74 - description: memory read client 75 - description: memory write client 76 77 interconnect-names: 78 items: 79 - const: dma-mem # read 80 - const: write 81 82 iommus: 83 maxItems: 1 84 85 operating-points-v2: true 86 87 power-domains: 88 items: 89 - description: phandle to the core power domain 90 91 nvidia,default-tap: 92 description: Specify the default inbound sampling clock trimmer value for 93 non-tunable modes. 94 95 The values are used for compensating trace length differences by 96 adjusting the sampling point. The values are programmed to the Vendor 97 Clock Control Register. Please refer to the reference manual of the SoC 98 for correct values. 99 100 The DQS trim values are only used on controllers which support HS400 101 timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400. 102 $ref: /schemas/types.yaml#/definitions/uint32 103 104 nvidia,default-trim: 105 description: Specify the default outbound clock trimmer value. 106 $ref: /schemas/types.yaml#/definitions/uint32 107 108 nvidia,dqs-trim: 109 description: Specify DQS trim value for HS400 timing. 110 $ref: /schemas/types.yaml#/definitions/uint32 111 112 nvidia,pad-autocal-pull-down-offset-1v8: 113 description: Specify drive strength calibration offsets for 1.8 V 114 signaling modes. 115 $ref: /schemas/types.yaml#/definitions/uint32 116 117 nvidia,pad-autocal-pull-down-offset-1v8-timeout: 118 description: Specify drive strength used as a fallback in case the 119 automatic calibration times out on a 1.8 V signaling mode. 120 $ref: /schemas/types.yaml#/definitions/uint32 121 122 nvidia,pad-autocal-pull-down-offset-3v3: 123 description: Specify drive strength calibration offsets for 3.3 V 124 signaling modes. 125 $ref: /schemas/types.yaml#/definitions/uint32 126 127 nvidia,pad-autocal-pull-down-offset-3v3-timeout: 128 description: Specify drive strength used as a fallback in case the 129 automatic calibration times out on a 3.3 V signaling mode. 130 $ref: /schemas/types.yaml#/definitions/uint32 131 132 nvidia,pad-autocal-pull-down-offset-sdr104: 133 description: Specify drive strength calibration offsets for SDR104 mode. 134 $ref: /schemas/types.yaml#/definitions/uint32 135 136 nvidia,pad-autocal-pull-down-offset-hs400: 137 description: Specify drive strength calibration offsets for HS400 mode. 138 $ref: /schemas/types.yaml#/definitions/uint32 139 140 nvidia,pad-autocal-pull-up-offset-1v8: 141 description: Specify drive strength calibration offsets for 1.8 V 142 signaling modes. 143 $ref: /schemas/types.yaml#/definitions/uint32 144 145 nvidia,pad-autocal-pull-up-offset-1v8-timeout: 146 description: Specify drive strength used as a fallback in case the 147 automatic calibration times out on a 1.8 V signaling mode. 148 $ref: /schemas/types.yaml#/definitions/uint32 149 150 nvidia,pad-autocal-pull-up-offset-3v3: 151 description: Specify drive strength calibration offsets for 3.3 V 152 signaling modes. 153 154 The property values are drive codes which are programmed into the 155 PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG 156 register. A higher value corresponds to higher drive strength. Please 157 refer to the reference manual of the SoC for correct values. The SDR104 158 and HS400 timing specific values are used in corresponding modes if 159 specified. 160 $ref: /schemas/types.yaml#/definitions/uint32 161 162 nvidia,pad-autocal-pull-up-offset-3v3-timeout: 163 description: Specify drive strength used as a fallback in case the 164 automatic calibration times out on a 3.3 V signaling mode. 165 $ref: /schemas/types.yaml#/definitions/uint32 166 167 nvidia,pad-autocal-pull-up-offset-sdr104: 168 description: Specify drive strength calibration offsets for SDR104 mode. 169 $ref: /schemas/types.yaml#/definitions/uint32 170 171 nvidia,pad-autocal-pull-up-offset-hs400: 172 description: Specify drive strength calibration offsets for HS400 mode. 173 $ref: /schemas/types.yaml#/definitions/uint32 174 175 nvidia,only-1-8v: 176 description: The presence of this property indicates that the controller 177 operates at a 1.8 V fixed I/O voltage. 178 $ref: /schemas/types.yaml#/definitions/flag 179 180required: 181 - compatible 182 - reg 183 - interrupts 184 - clocks 185 - resets 186 - reset-names 187 188allOf: 189 - $ref: mmc-controller.yaml 190 - if: 191 properties: 192 compatible: 193 contains: 194 enum: 195 - nvidia,tegra20-sdhci 196 - nvidia,tegra30-sdhci 197 - nvidia,tegra114-sdhci 198 - nvidia,tegra124-sdhci 199 then: 200 properties: 201 clocks: 202 items: 203 - description: module clock 204 else: 205 properties: 206 clocks: 207 items: 208 - description: module clock 209 - description: timeout clock 210 211 clock-names: 212 items: 213 - const: sdhci 214 - const: tmclk 215 required: 216 - clock-names 217 218 - if: 219 properties: 220 compatible: 221 contains: 222 const: nvidia,tegra210-sdhci 223 then: 224 properties: 225 pinctrl-names: 226 oneOf: 227 - items: 228 - const: sdmmc-3v3 229 description: pad configuration for 3.3 V 230 - const: sdmmc-1v8 231 description: pad configuration for 1.8 V 232 - const: sdmmc-3v3-drv 233 description: pull-up/down configuration for 3.3 V 234 - const: sdmmc-1v8-drv 235 description: pull-up/down configuration for 1.8 V 236 - items: 237 - const: sdmmc-3v3-drv 238 description: pull-up/down configuration for 3.3 V 239 - const: sdmmc-1v8-drv 240 description: pull-up/down configuration for 1.8 V 241 - items: 242 - const: sdmmc-1v8-drv 243 description: pull-up/down configuration for 1.8 V 244 required: 245 - clock-names 246 - if: 247 properties: 248 compatible: 249 contains: 250 enum: 251 - nvidia,tegra186-sdhci 252 - nvidia,tegra194-sdhci 253 then: 254 properties: 255 pinctrl-names: 256 items: 257 - const: sdmmc-3v3 258 description: pad configuration for 3.3 V 259 - const: sdmmc-1v8 260 description: pad configuration for 1.8 V 261 required: 262 - clock-names 263 264unevaluatedProperties: false 265 266examples: 267 - | 268 #include <dt-bindings/interrupt-controller/arm-gic.h> 269 270 mmc@c8000200 { 271 compatible = "nvidia,tegra20-sdhci"; 272 reg = <0xc8000200 0x200>; 273 interrupts = <47>; 274 clocks = <&tegra_car 14>; 275 resets = <&tegra_car 14>; 276 reset-names = "sdhci"; 277 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 278 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 279 power-gpios = <&gpio 155 0>; /* gpio PT3 */ 280 bus-width = <8>; 281 }; 282 283 - | 284 #include <dt-bindings/clock/tegra210-car.h> 285 #include <dt-bindings/interrupt-controller/arm-gic.h> 286 287 mmc@700b0000 { 288 compatible = "nvidia,tegra210-sdhci"; 289 reg = <0x700b0000 0x200>; 290 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, 292 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 293 clock-names = "sdhci", "tmclk"; 294 resets = <&tegra_car 14>; 295 reset-names = "sdhci"; 296 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 297 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 298 pinctrl-0 = <&sdmmc1_3v3>; 299 pinctrl-1 = <&sdmmc1_1v8>; 300 pinctrl-2 = <&sdmmc1_3v3_drv>; 301 pinctrl-3 = <&sdmmc1_1v8_drv>; 302 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 303 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 304 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 305 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 306 nvidia,default-tap = <0x2>; 307 nvidia,default-trim = <0x4>; 308 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 309 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 310 <&tegra_car TEGRA210_CLK_PLL_C4>; 311 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 312 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 313 }; 314