xref: /freebsd/sys/contrib/device-tree/Bindings/mmc/mtk-sd.yaml (revision 535af610a4fdace6d50960c0ad9be0597eea7a1b) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MTK MSDC Storage Host Controller
8
9maintainers:
10  - Chaotian Jing <chaotian.jing@mediatek.com>
11  - Wenbin Mei <wenbin.mei@mediatek.com>
12
13properties:
14  compatible:
15    oneOf:
16      - enum:
17          - mediatek,mt2701-mmc
18          - mediatek,mt2712-mmc
19          - mediatek,mt6779-mmc
20          - mediatek,mt6795-mmc
21          - mediatek,mt7620-mmc
22          - mediatek,mt7622-mmc
23          - mediatek,mt7986-mmc
24          - mediatek,mt8135-mmc
25          - mediatek,mt8173-mmc
26          - mediatek,mt8183-mmc
27          - mediatek,mt8516-mmc
28      - items:
29          - const: mediatek,mt7623-mmc
30          - const: mediatek,mt2701-mmc
31      - items:
32          - enum:
33              - mediatek,mt8186-mmc
34              - mediatek,mt8188-mmc
35              - mediatek,mt8192-mmc
36              - mediatek,mt8195-mmc
37              - mediatek,mt8365-mmc
38          - const: mediatek,mt8183-mmc
39
40  reg:
41    minItems: 1
42    items:
43      - description: base register (required).
44      - description: top base register (required for MT8183).
45
46  clocks:
47    description:
48      Should contain phandle for the clock feeding the MMC controller.
49    minItems: 2
50    maxItems: 7
51
52  clock-names:
53    minItems: 2
54    maxItems: 7
55
56  interrupts:
57    description:
58      Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
59      interrupt is required and be configured as wakeup source irq.
60    minItems: 1
61    maxItems: 2
62
63  interrupt-names:
64    items:
65      - const: msdc
66      - const: sdio_wakeup
67
68  pinctrl-names:
69    description:
70      Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
71      will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this
72      scenario.
73    minItems: 2
74    items:
75      - const: default
76      - const: state_uhs
77      - const: state_eint
78
79  pinctrl-0:
80    description:
81      should contain default/high speed pin ctrl.
82    maxItems: 1
83
84  pinctrl-1:
85    description:
86      should contain uhs mode pin ctrl.
87    maxItems: 1
88
89  pinctrl-2:
90    description:
91      should switch dat1 pin to GPIO mode.
92    maxItems: 1
93
94  assigned-clocks:
95    description:
96      PLL of the source clock.
97    maxItems: 1
98
99  assigned-clock-parents:
100    description:
101      parent of source clock, used for HS400 mode to get 400Mhz source clock.
102    maxItems: 1
103
104  hs400-ds-delay:
105    $ref: /schemas/types.yaml#/definitions/uint32
106    description:
107      HS400 DS delay setting.
108    minimum: 0
109    maximum: 0xffffffff
110
111  mediatek,hs200-cmd-int-delay:
112    $ref: /schemas/types.yaml#/definitions/uint32
113    description:
114      HS200 command internal delay setting.
115      This field has total 32 stages.
116      The value is an integer from 0 to 31.
117    minimum: 0
118    maximum: 31
119
120  mediatek,hs400-cmd-int-delay:
121    $ref: /schemas/types.yaml#/definitions/uint32
122    description:
123      HS400 command internal delay setting.
124      This field has total 32 stages.
125      The value is an integer from 0 to 31.
126    minimum: 0
127    maximum: 31
128
129  mediatek,hs400-cmd-resp-sel-rising:
130    $ref: /schemas/types.yaml#/definitions/flag
131    description:
132      HS400 command response sample selection.
133      If present, HS400 command responses are sampled on rising edges.
134      If not present, HS400 command responses are sampled on falling edges.
135
136  mediatek,hs400-ds-dly3:
137    $ref: /schemas/types.yaml#/definitions/uint32
138    description:
139      Gear of the third delay line for DS for input data latch in data
140      pad macro, there are 32 stages from 0 to 31.
141      For different corner IC, the time is different about one step, it is
142      about 100ps.
143      The value is confirmed by doing scan and calibration to find a best
144      value with corner IC and it is valid only for HS400 mode.
145    minimum: 0
146    maximum: 31
147
148  mediatek,latch-ck:
149    $ref: /schemas/types.yaml#/definitions/uint32
150    description:
151      Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
152      data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
153      if not present, default value is 0.
154      applied to compatible "mediatek,mt2701-mmc".
155    minimum: 0
156    maximum: 7
157
158  resets:
159    maxItems: 1
160
161  reset-names:
162    const: hrst
163
164required:
165  - compatible
166  - reg
167  - interrupts
168  - clocks
169  - clock-names
170  - pinctrl-names
171  - pinctrl-0
172  - pinctrl-1
173  - vmmc-supply
174  - vqmmc-supply
175
176allOf:
177  - $ref: mmc-controller.yaml#
178  - if:
179      properties:
180        compatible:
181          enum:
182            - mediatek,mt2701-mmc
183            - mediatek,mt6779-mmc
184            - mediatek,mt6795-mmc
185            - mediatek,mt7620-mmc
186            - mediatek,mt7622-mmc
187            - mediatek,mt7623-mmc
188            - mediatek,mt8135-mmc
189            - mediatek,mt8173-mmc
190            - mediatek,mt8183-mmc
191            - mediatek,mt8186-mmc
192            - mediatek,mt8188-mmc
193            - mediatek,mt8195-mmc
194            - mediatek,mt8516-mmc
195    then:
196      properties:
197        clocks:
198          minItems: 2
199          items:
200            - description: source clock
201            - description: HCLK which used for host
202            - description: independent source clock gate
203        clock-names:
204          minItems: 2
205          items:
206            - const: source
207            - const: hclk
208            - const: source_cg
209
210  - if:
211      properties:
212        compatible:
213          contains:
214            const: mediatek,mt2712-mmc
215    then:
216      properties:
217        clocks:
218          minItems: 3
219          items:
220            - description: source clock
221            - description: HCLK which used for host
222            - description: independent source clock gate
223            - description: bus clock used for internal register access (required for MSDC0/3).
224        clock-names:
225          minItems: 3
226          items:
227            - const: source
228            - const: hclk
229            - const: source_cg
230            - const: bus_clk
231
232  - if:
233      properties:
234        compatible:
235          contains:
236            const: mediatek,mt8183-mmc
237    then:
238      properties:
239        reg:
240          minItems: 2
241
242  - if:
243      properties:
244        compatible:
245          contains:
246            enum:
247              - mediatek,mt7986-mmc
248    then:
249      properties:
250        clocks:
251          minItems: 3
252          items:
253            - description: source clock
254            - description: HCLK which used for host
255            - description: independent source clock gate
256            - description: bus clock used for internal register access (required for MSDC0/3).
257            - description: msdc subsys clock gate
258        clock-names:
259          minItems: 3
260          items:
261            - const: source
262            - const: hclk
263            - const: source_cg
264            - const: bus_clk
265            - const: sys_cg
266
267  - if:
268      properties:
269        compatible:
270          enum:
271            - mediatek,mt8186-mmc
272            - mediatek,mt8188-mmc
273            - mediatek,mt8195-mmc
274    then:
275      properties:
276        clocks:
277          items:
278            - description: source clock
279            - description: HCLK which used for host
280            - description: independent source clock gate
281            - description: crypto clock used for data encrypt/decrypt (optional)
282        clock-names:
283          items:
284            - const: source
285            - const: hclk
286            - const: source_cg
287            - const: crypto
288
289  - if:
290      properties:
291        compatible:
292          contains:
293            const: mediatek,mt8192-mmc
294    then:
295      properties:
296        clocks:
297          items:
298            - description: source clock
299            - description: HCLK which used for host
300            - description: independent source clock gate
301            - description: msdc subsys clock gate
302            - description: peripheral bus clock gate
303            - description: AXI bus clock gate
304            - description: AHB bus clock gate
305        clock-names:
306          items:
307            - const: source
308            - const: hclk
309            - const: source_cg
310            - const: sys_cg
311            - const: pclk_cg
312            - const: axi_cg
313            - const: ahb_cg
314
315unevaluatedProperties: false
316
317examples:
318  - |
319    #include <dt-bindings/interrupt-controller/irq.h>
320    #include <dt-bindings/interrupt-controller/arm-gic.h>
321    #include <dt-bindings/clock/mt8173-clk.h>
322    mmc0: mmc@11230000 {
323        compatible = "mediatek,mt8173-mmc";
324        reg = <0x11230000 0x1000>;
325        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
326        vmmc-supply = <&mt6397_vemc_3v3_reg>;
327        vqmmc-supply = <&mt6397_vio18_reg>;
328        clocks = <&pericfg CLK_PERI_MSDC30_0>,
329                 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
330        clock-names = "source", "hclk";
331        pinctrl-names = "default", "state_uhs";
332        pinctrl-0 = <&mmc0_pins_default>;
333        pinctrl-1 = <&mmc0_pins_uhs>;
334        assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
335        assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
336        hs400-ds-delay = <0x14015>;
337        mediatek,hs200-cmd-int-delay = <26>;
338        mediatek,hs400-cmd-int-delay = <14>;
339        mediatek,hs400-cmd-resp-sel-rising;
340    };
341
342    mmc3: mmc@11260000 {
343        compatible = "mediatek,mt8173-mmc";
344        reg = <0x11260000 0x1000>;
345        clock-names = "source", "hclk";
346        clocks = <&pericfg CLK_PERI_MSDC30_3>,
347                 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
348        interrupt-names = "msdc", "sdio_wakeup";
349        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
350                     <&pio 23 IRQ_TYPE_LEVEL_LOW>;
351        pinctrl-names = "default", "state_uhs", "state_eint";
352        pinctrl-0 = <&mmc2_pins_default>;
353        pinctrl-1 = <&mmc2_pins_uhs>;
354        pinctrl-2 = <&mmc2_pins_eint>;
355        bus-width = <4>;
356        max-frequency = <200000000>;
357        cap-sd-highspeed;
358        sd-uhs-sdr104;
359        keep-power-in-suspend;
360        wakeup-source;
361        cap-sdio-irq;
362        no-mmc;
363        no-sd;
364        non-removable;
365        vmmc-supply = <&sdio_fixed_3v3>;
366        vqmmc-supply = <&mt6397_vgp3_reg>;
367        mmc-pwrseq = <&wifi_pwrseq>;
368    };
369
370...
371