1* ARM PrimeCell MultiMedia Card Interface (MMCI) PL180/1 2 3The ARM PrimeCell MMCI PL180 and PL181 provides an interface for 4reading and writing to MultiMedia and SD cards alike. 5 6This file documents differences between the core properties described 7by mmc.txt and the properties used by the mmci driver. Using "st" as 8the prefix for a property, indicates support by the ST Micro variant. 9 10Required properties: 11- compatible : contains "arm,pl18x", "arm,primecell". 12- vmmc-supply : phandle to the regulator device tree node, mentioned 13 as the VCC/VDD supply in the eMMC/SD specs. 14 15Optional properties: 16- arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides 17 the ID provided by the HW 18- resets : phandle to internal reset line. 19 Should be defined for sdmmc variant. 20- vqmmc-supply : phandle to the regulator device tree node, mentioned 21 as the VCCQ/VDD_IO supply in the eMMC/SD specs. 22specific for ux500 variant: 23- st,sig-dir-dat0 : bus signal direction pin used for DAT[0]. 24- st,sig-dir-dat2 : bus signal direction pin used for DAT[2]. 25- st,sig-dir-dat31 : bus signal direction pin used for DAT[3] and DAT[1]. 26- st,sig-dir-dat74 : bus signal direction pin used for DAT[4] to DAT[7]. 27- st,sig-dir-cmd : cmd signal direction pin used for CMD. 28- st,sig-pin-fbclk : feedback clock signal pin used. 29 30specific for sdmmc variant: 31- reg : a second base register may be defined if a delay 32 block is present and used for tuning. 33- st,sig-dir : signal direction polarity used for cmd, dat0 dat123. 34- st,neg-edge : data & command phase relation, generated on 35 sd clock falling edge. 36- st,use-ckin : use ckin pin from an external driver to sample 37 the receive data (example: with voltage 38 switch transceiver). 39 40Deprecated properties: 41- mmc-cap-mmc-highspeed : indicates whether MMC is high speed capable. 42- mmc-cap-sd-highspeed : indicates whether SD is high speed capable. 43 44Example: 45 46sdi0_per1@80126000 { 47 compatible = "arm,pl18x", "arm,primecell"; 48 reg = <0x80126000 0x1000>; 49 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; 50 51 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ 52 <&dma 29 0 0x0>; /* Logical - MemToDev */ 53 dma-names = "rx", "tx"; 54 55 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; 56 clock-names = "sdi", "apb_pclk"; 57 58 max-frequency = <100000000>; 59 bus-width = <4>; 60 cap-sd-highspeed; 61 cap-mmc-highspeed; 62 cd-gpios = <&gpio2 31 0x4>; // 95 63 st,sig-dir-dat0; 64 st,sig-dir-dat2; 65 st,sig-dir-cmd; 66 st,sig-pin-fbclk; 67 68 vmmc-supply = <&ab8500_ldo_aux3_reg>; 69 vqmmc-supply = <&vmmci>; 70 71 pinctrl-names = "default", "sleep"; 72 pinctrl-0 = <&sdi0_default_mode>; 73 pinctrl-1 = <&sdi0_sleep_mode>; 74}; 75