1Marvell Xenon SDHCI Controller device tree bindings 2This file documents differences between the core mmc properties 3described by mmc.txt and the properties used by the Xenon implementation. 4 5Multiple SDHCs might be put into a single Xenon IP, to save size and cost. 6Each SDHC is independent and owns independent resources, such as register sets, 7clock and PHY. 8Each SDHC should have an independent device tree node. 9 10Required Properties: 11- compatible: should be one of the following 12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC. 13 Must provide a second register area and marvell,pad-type. 14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806. 15 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110. 16 17- clocks: 18 Array of clocks required for SDHC. 19 Require at least input clock for Xenon IP core. For Armada AP806 and 20 CP110, the AXI clock is also mandatory. 21 22- clock-names: 23 Array of names corresponding to clocks property. 24 The input clock for Xenon IP core should be named as "core". 25 The input clock for the AXI bus must be named as "axi". 26 27- reg: 28 * For "marvell,armada-3700-sdhci", two register areas. 29 The first one for Xenon IP register. The second one for the Armada 3700 SoC 30 PHY PAD Voltage Control register. 31 Please follow the examples with compatible "marvell,armada-3700-sdhci" 32 in below. 33 Please also check property marvell,pad-type in below. 34 35 * For other compatible strings, one register area for Xenon IP. 36 37Optional Properties: 38- marvell,xenon-sdhc-id: 39 Indicate the corresponding bit index of current SDHC in 40 SDHC System Operation Control Register Bit[7:0]. 41 Set/clear the corresponding bit to enable/disable current SDHC. 42 If Xenon IP contains only one SDHC, this property is optional. 43 44- marvell,xenon-phy-type: 45 Xenon support multiple types of PHYs. 46 To select eMMC 5.1 PHY, set: 47 marvell,xenon-phy-type = "emmc 5.1 phy" 48 eMMC 5.1 PHY is the default choice if this property is not provided. 49 To select eMMC 5.0 PHY, set: 50 marvell,xenon-phy-type = "emmc 5.0 phy" 51 52 All those types of PHYs can support eMMC, SD and SDIO. 53 Please note that this property only presents the type of PHY. 54 It doesn't stand for the entire SDHC type or property. 55 For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only 56 supports eMMC 5.1. 57 58- marvell,xenon-phy-znr: 59 Set PHY ZNR value. 60 Only available for eMMC PHY. 61 Valid range = [0:0x1F]. 62 ZNR is set as 0xF by default if this property is not provided. 63 64- marvell,xenon-phy-zpr: 65 Set PHY ZPR value. 66 Only available for eMMC PHY. 67 Valid range = [0:0x1F]. 68 ZPR is set as 0xF by default if this property is not provided. 69 70- marvell,xenon-phy-nr-success-tun: 71 Set the number of required consecutive successful sampling points 72 used to identify a valid sampling window, in tuning process. 73 Valid range = [1:7]. 74 Set as 0x4 by default if this property is not provided. 75 76- marvell,xenon-phy-tun-step-divider: 77 Set the divider for calculating TUN_STEP. 78 Set as 64 by default if this property is not provided. 79 80- marvell,xenon-phy-slow-mode: 81 If this property is selected, transfers will bypass PHY. 82 Only available when bus frequency lower than 55MHz in SDR mode. 83 Disabled by default. Please only try this property if timing issues 84 always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25, 85 SD Default Speed and HS mode and eMMC legacy speed mode. 86 87- marvell,xenon-tun-count: 88 Xenon SDHC SoC usually doesn't provide re-tuning counter in 89 Capabilities Register 3 Bit[11:8]. 90 This property provides the re-tuning counter. 91 If this property is not set, default re-tuning counter will 92 be set as 0x9 in driver. 93 94- marvell,pad-type: 95 Type of Armada 3700 SoC PHY PAD Voltage Controller register. 96 Only valid when "marvell,armada-3700-sdhci" is selected. 97 Two types: "sd" and "fixed-1-8v". 98 If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning and is 99 switched to 1.8V when later in higher speed mode. 100 If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for eMMC. 101 Please follow the examples with compatible "marvell,armada-3700-sdhci" 102 in below. 103 104Example: 105- For eMMC: 106 107 sdhci@aa0000 { 108 compatible = "marvell,armada-ap806-sdhci"; 109 reg = <0xaa0000 0x1000>; 110 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH> 111 clocks = <&emmc_clk>,<&axi_clk>; 112 clock-names = "core", "axi"; 113 bus-width = <4>; 114 marvell,xenon-phy-slow-mode; 115 marvell,xenon-tun-count = <11>; 116 non-removable; 117 no-sd; 118 no-sdio; 119 120 /* Vmmc and Vqmmc are both fixed */ 121 }; 122 123- For SD/SDIO: 124 125 sdhci@ab0000 { 126 compatible = "marvell,armada-cp110-sdhci"; 127 reg = <0xab0000 0x1000>; 128 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH> 129 vqmmc-supply = <&sd_vqmmc_regulator>; 130 vmmc-supply = <&sd_vmmc_regulator>; 131 clocks = <&sdclk>, <&axi_clk>; 132 clock-names = "core", "axi"; 133 bus-width = <4>; 134 marvell,xenon-tun-count = <9>; 135 }; 136 137- For eMMC with compatible "marvell,armada-3700-sdhci": 138 139 sdhci@aa0000 { 140 compatible = "marvell,armada-3700-sdhci"; 141 reg = <0xaa0000 0x1000>, 142 <phy_addr 0x4>; 143 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH> 144 clocks = <&emmcclk>; 145 clock-names = "core"; 146 bus-width = <8>; 147 mmc-ddr-1_8v; 148 mmc-hs400-1_8v; 149 non-removable; 150 no-sd; 151 no-sdio; 152 153 /* Vmmc and Vqmmc are both fixed */ 154 155 marvell,pad-type = "fixed-1-8v"; 156 }; 157 158- For SD/SDIO with compatible "marvell,armada-3700-sdhci": 159 160 sdhci@ab0000 { 161 compatible = "marvell,armada-3700-sdhci"; 162 reg = <0xab0000 0x1000>, 163 <phy_addr 0x4>; 164 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH> 165 vqmmc-supply = <&sd_regulator>; 166 /* Vmmc is fixed */ 167 clocks = <&sdclk>; 168 clock-names = "core"; 169 bus-width = <4>; 170 171 marvell,pad-type = "sd"; 172 }; 173