xref: /freebsd/sys/contrib/device-tree/Bindings/mmc/fsl-imx-esdhc.yaml (revision b197d4b893974c9eb4d7b38704c6d5c486235d6f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
8
9maintainers:
10  - Shawn Guo <shawnguo@kernel.org>
11
12allOf:
13  - $ref: "mmc-controller.yaml"
14
15description: |
16  The Enhanced Secure Digital Host Controller on Freescale i.MX family
17  provides an interface for MMC, SD, and SDIO types of memory cards.
18
19  This file documents differences between the core properties described
20  by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - fsl,imx25-esdhc
27          - fsl,imx35-esdhc
28          - fsl,imx51-esdhc
29          - fsl,imx53-esdhc
30          - fsl,imx6q-usdhc
31          - fsl,imx6sl-usdhc
32          - fsl,imx6sll-usdhc
33          - fsl,imx6sx-usdhc
34          - fsl,imx6ull-usdhc
35          - fsl,imx7d-usdhc
36          - fsl,imx7ulp-usdhc
37          - fsl,imxrt1050-usdhc
38          - nxp,s32g2-usdhc
39      - items:
40          - enum:
41              - fsl,imx8mm-usdhc
42              - fsl,imx8mn-usdhc
43              - fsl,imx8mp-usdhc
44              - fsl,imx8mq-usdhc
45              - fsl,imx8qm-usdhc
46              - fsl,imx8qxp-usdhc
47          - const: fsl,imx7d-usdhc
48      - items:
49          - enum:
50              - fsl,imx93-usdhc
51              - fsl,imx8ulp-usdhc
52          - const: fsl,imx8mm-usdhc
53
54  reg:
55    maxItems: 1
56
57  interrupts:
58    maxItems: 1
59
60  fsl,wp-controller:
61    description: |
62      boolean, if present, indicate to use controller internal write protection.
63    type: boolean
64
65  fsl,delay-line:
66    $ref: /schemas/types.yaml#/definitions/uint32
67    description: |
68      Specify the number of delay cells for override mode.
69      This is used to set the clock delay for DLL(Delay Line) on override mode
70      to select a proper data sampling window in case the clock quality is not good
71      due to signal path is too long on the board. Please refer to eSDHC/uSDHC
72      chapter, DLL (Delay Line) section in RM for details.
73    default: 0
74
75  voltage-ranges:
76    $ref: '/schemas/types.yaml#/definitions/uint32-matrix'
77    description: |
78      Specify the voltage range in case there are software transparent level
79      shifters on the outputs of the controller. Two cells are required, first
80      cell specifies minimum slot voltage (mV), second cell specifies maximum
81      slot voltage (mV).
82    items:
83      items:
84        - description: value for minimum slot voltage
85        - description: value for maximum slot voltage
86    maxItems: 1
87
88  fsl,tuning-start-tap:
89    $ref: /schemas/types.yaml#/definitions/uint32
90    description: |
91      Specify the start delay cell point when send first CMD19 in tuning procedure.
92    default: 0
93
94  fsl,tuning-step:
95    $ref: /schemas/types.yaml#/definitions/uint32
96    description: |
97      Specify the increasing delay cell steps in tuning procedure.
98      The uSDHC use one delay cell as default increasing step to do tuning process.
99      This property allows user to change the tuning step to more than one delay
100      cells which is useful for some special boards or cards when the default
101      tuning step can't find the proper delay window within limited tuning retries.
102    default: 0
103
104  fsl,strobe-dll-delay-target:
105    $ref: /schemas/types.yaml#/definitions/uint32
106    description: |
107      Specify the strobe dll control slave delay target.
108      This delay target programming host controller loopback read clock, and this
109      property allows user to change the delay target for the strobe input read clock.
110      If not use this property, driver default set the delay target to value 7.
111      Only eMMC HS400 mode need to take care of this property.
112    default: 0
113
114  clocks:
115    maxItems: 3
116    description:
117      Handle clocks for the sdhc controller.
118
119  clock-names:
120    items:
121      - const: ipg
122      - const: ahb
123      - const: per
124
125  power-domains:
126    maxItems: 1
127
128  pinctrl-names:
129    oneOf:
130      - minItems: 3
131        items:
132          - const: default
133          - const: state_100mhz
134          - const: state_200mhz
135          - const: sleep
136      - minItems: 1
137        items:
138          - const: default
139          - const: sleep
140
141required:
142  - compatible
143  - reg
144  - interrupts
145
146unevaluatedProperties: false
147
148examples:
149  - |
150    mmc@70004000 {
151        compatible = "fsl,imx51-esdhc";
152        reg = <0x70004000 0x4000>;
153        interrupts = <1>;
154        fsl,wp-controller;
155    };
156
157    mmc@70008000 {
158        compatible = "fsl,imx51-esdhc";
159        reg = <0x70008000 0x4000>;
160        interrupts = <2>;
161        cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
162        wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
163    };
164