xref: /freebsd/sys/contrib/device-tree/Bindings/mmc/cdns,sdhci.yaml (revision d0b2dbfa0ecf2bbc9709efc5e20baf8e4b44bbbf) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
8
9maintainers:
10  - Masahiro Yamada <yamada.masahiro@socionext.com>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - amd,pensando-elba-sd4hc
17          - microchip,mpfs-sd4hc
18          - socionext,uniphier-sd4hc
19      - const: cdns,sd4hc
20
21  reg:
22    minItems: 1
23    maxItems: 2
24
25  interrupts:
26    maxItems: 1
27
28  clocks:
29    maxItems: 1
30
31  resets:
32    maxItems: 1
33
34  # PHY DLL input delays:
35  # They are used to delay the data valid window, and align the window to
36  # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
37  # and it is increased by 2.5ns in each step.
38
39  cdns,phy-input-delay-sd-highspeed:
40    description: Value of the delay in the input path for SD high-speed timing
41    $ref: /schemas/types.yaml#/definitions/uint32
42    minimum: 0
43    maximum: 0x1f
44
45  cdns,phy-input-delay-legacy:
46    description: Value of the delay in the input path for legacy timing
47    $ref: /schemas/types.yaml#/definitions/uint32
48    minimum: 0
49    maximum: 0x1f
50
51  cdns,phy-input-delay-sd-uhs-sdr12:
52    description: Value of the delay in the input path for SD UHS SDR12 timing
53    $ref: /schemas/types.yaml#/definitions/uint32
54    minimum: 0
55    maximum: 0x1f
56
57  cdns,phy-input-delay-sd-uhs-sdr25:
58    description: Value of the delay in the input path for SD UHS SDR25 timing
59    $ref: /schemas/types.yaml#/definitions/uint32
60    minimum: 0
61    maximum: 0x1f
62
63  cdns,phy-input-delay-sd-uhs-sdr50:
64    description: Value of the delay in the input path for SD UHS SDR50 timing
65    $ref: /schemas/types.yaml#/definitions/uint32
66    minimum: 0
67    maximum: 0x1f
68
69  cdns,phy-input-delay-sd-uhs-ddr50:
70    description: Value of the delay in the input path for SD UHS DDR50 timing
71    $ref: /schemas/types.yaml#/definitions/uint32
72    minimum: 0
73    maximum: 0x1f
74
75  cdns,phy-input-delay-mmc-highspeed:
76    description: Value of the delay in the input path for MMC high-speed timing
77    $ref: /schemas/types.yaml#/definitions/uint32
78    minimum: 0
79    maximum: 0x1f
80
81  cdns,phy-input-delay-mmc-ddr:
82    description: Value of the delay in the input path for eMMC high-speed DDR timing
83
84  # PHY DLL clock delays:
85  # Each delay property represents the fraction of the clock period.
86  # The approximate delay value will be
87  # (<delay property value>/128)*sdmclk_clock_period.
88    $ref: /schemas/types.yaml#/definitions/uint32
89    minimum: 0
90    maximum: 0x1f
91
92  cdns,phy-dll-delay-sdclk:
93    description: |
94      Value of the delay introduced on the sdclk output for all modes except
95      HS200, HS400 and HS400_ES.
96    $ref: /schemas/types.yaml#/definitions/uint32
97    minimum: 0
98    maximum: 0x7f
99
100  cdns,phy-dll-delay-sdclk-hsmmc:
101    description: |
102      Value of the delay introduced on the sdclk output for HS200, HS400 and
103      HS400_ES speed modes.
104    $ref: /schemas/types.yaml#/definitions/uint32
105    minimum: 0
106    maximum: 0x7f
107
108  cdns,phy-dll-delay-strobe:
109    description: |
110      Value of the delay introduced on the dat_strobe input used in
111      HS400 / HS400_ES speed modes.
112    $ref: /schemas/types.yaml#/definitions/uint32
113    minimum: 0
114    maximum: 0x7f
115
116required:
117  - compatible
118  - reg
119  - interrupts
120  - clocks
121
122allOf:
123  - $ref: mmc-controller.yaml
124  - if:
125      properties:
126        compatible:
127          contains:
128            const: amd,pensando-elba-sd4hc
129    then:
130      properties:
131        reg:
132          items:
133            - description: Host controller registers
134            - description: Elba byte-lane enable register for writes
135      required:
136        - resets
137    else:
138      properties:
139        reg:
140          maxItems: 1
141
142unevaluatedProperties: false
143
144examples:
145  - |
146    emmc: mmc@5a000000 {
147        compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
148        reg = <0x5a000000 0x400>;
149        interrupts = <0 78 4>;
150        clocks = <&clk 4>;
151        bus-width = <8>;
152        mmc-ddr-1_8v;
153        mmc-hs200-1_8v;
154        mmc-hs400-1_8v;
155        cdns,phy-dll-delay-sdclk = <0>;
156    };
157