xref: /freebsd/sys/contrib/device-tree/Bindings/mmc/arm,pl18x.yaml (revision 924226fba12cc9a228c73b956e1b7fa24c60b055) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/arm,pl18x.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM PrimeCell MultiMedia Card Interface (MMCI) PL180 and PL181
8
9maintainers:
10  - Linus Walleij <linus.walleij@linaro.org>
11  - Ulf Hansson <ulf.hansson@linaro.org>
12
13description:
14  The ARM PrimeCells MMCI PL180 and PL181 provides an interface for
15  reading and writing to MultiMedia and SD cards alike. Over the years
16  vendors have use the VHDL code from ARM to create derivative MMC/SD/SDIO
17  host controllers with very similar characteristics.
18
19allOf:
20  - $ref: /schemas/arm/primecell.yaml#
21  - $ref: mmc-controller.yaml#
22
23# We need a select here so we don't match all nodes with 'arm,primecell'
24select:
25  properties:
26    compatible:
27      contains:
28        enum:
29          - arm,pl180
30          - arm,pl181
31          - arm,pl18x
32  required:
33    - compatible
34
35properties:
36  compatible:
37    oneOf:
38      - description: The first version of the block, simply called
39          PL180 and found in the ARM Integrator IM/PD1 logic module.
40        items:
41          - const: arm,pl180
42          - const: arm,primecell
43      - description: The improved version of the block, found in the
44          ARM Versatile and later reference designs. Further revisions
45          exist but get detected at runtime by reading some magic numbers
46          in the PrimeCell ID registers.
47        items:
48          - const: arm,pl181
49          - const: arm,primecell
50      - description: Wildcard entry that will let the operating system
51          inspect the PrimeCell ID registers to determine which hardware
52          variant of PL180 or PL181 this is.
53        items:
54          - const: arm,pl18x
55          - const: arm,primecell
56
57  clocks:
58    description: One or two clocks, the "apb_pclk" and the "MCLK"
59      which is the core block clock. The names are not compulsory.
60    minItems: 1
61    maxItems: 2
62
63  power-domains: true
64
65  resets:
66    maxItems: 1
67
68  reg:
69    description: the MMIO memory window must be exactly 4KB (0x1000) and the
70      layout should provide the PrimeCell ID registers so that the device can
71      be discovered. On ST Micro variants, a second register window may be
72      defined if a delay block is present and used for tuning.
73
74  interrupts:
75    description: The first interrupt is the command interrupt and corresponds
76      to the event at the end of a command. The second interrupt is the
77      PIO (polled I/O) interrupt and occurs when the FIFO needs to be
78      emptied as part of a bulk read from the card. Some variants have these
79      two interrupts wired into the same line (logic OR) and in that case
80      only one interrupt may be provided.
81    minItems: 1
82    maxItems: 2
83
84  st,sig-dir-dat0:
85    $ref: /schemas/types.yaml#/definitions/flag
86    description: ST Micro-specific property, bus signal direction pins used for
87      DAT[0].
88
89  st,sig-dir-dat2:
90    $ref: /schemas/types.yaml#/definitions/flag
91    description: ST Micro-specific property, bus signal direction pins used for
92      DAT[2].
93
94  st,sig-dir-dat31:
95    $ref: /schemas/types.yaml#/definitions/flag
96    description: ST Micro-specific property, bus signal direction pins used for
97      DAT[3] and DAT[1].
98
99  st,sig-dir-dat74:
100    $ref: /schemas/types.yaml#/definitions/flag
101    description: ST Micro-specific property, bus signal direction pins used for
102      DAT[7] and DAT[4].
103
104  st,sig-dir-cmd:
105    $ref: /schemas/types.yaml#/definitions/flag
106    description: ST Micro-specific property, CMD signal direction used for
107      pin CMD.
108
109  st,sig-pin-fbclk:
110    $ref: /schemas/types.yaml#/definitions/flag
111    description: ST Micro-specific property, feedback clock FBCLK signal pin
112      in use.
113
114  st,sig-dir:
115    $ref: /schemas/types.yaml#/definitions/flag
116    description: ST Micro-specific property, signal direction polarity used for
117      pins CMD, DAT[0], DAT[1], DAT[2] and DAT[3].
118
119  st,neg-edge:
120    $ref: /schemas/types.yaml#/definitions/flag
121    description: ST Micro-specific property, data and command phase relation,
122      generated on the sd clock falling edge.
123
124  st,use-ckin:
125    $ref: /schemas/types.yaml#/definitions/flag
126    description: ST Micro-specific property, use CKIN pin from an external
127      driver to sample the receive data (for example with a voltage switch
128      transceiver).
129
130  st,cmd-gpios:
131    maxItems: 1
132    description:
133      The GPIO matching the CMD pin.
134
135  st,ck-gpios:
136    maxItems: 1
137    description:
138      The GPIO matching the CK pin.
139
140  st,ckin-gpios:
141    maxItems: 1
142    description:
143      The GPIO matching the CKIN pin.
144
145dependencies:
146  st,cmd-gpios: [ "st,use-ckin" ]
147  st,ck-gpios: [ "st,use-ckin" ]
148  st,ckin-gpios: [ "st,use-ckin" ]
149
150unevaluatedProperties: false
151
152required:
153  - compatible
154  - reg
155  - interrupts
156
157examples:
158  - |
159    #include <dt-bindings/interrupt-controller/irq.h>
160    #include <dt-bindings/gpio/gpio.h>
161
162    mmc@5000 {
163      compatible = "arm,pl180", "arm,primecell";
164      reg = <0x5000 0x1000>;
165      interrupts-extended = <&vic 22 &sic 1>;
166      clocks = <&xtal24mhz>, <&pclk>;
167      clock-names = "mclk", "apb_pclk";
168    };
169
170    mmc@80126000 {
171      compatible = "arm,pl18x", "arm,primecell";
172      reg = <0x80126000 0x1000>;
173      interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
174      dmas = <&dma 29 0 0x2>, <&dma 29 0 0x0>;
175      dma-names = "rx", "tx";
176      clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
177      clock-names = "sdi", "apb_pclk";
178      max-frequency = <100000000>;
179      bus-width = <4>;
180      cap-sd-highspeed;
181      cap-mmc-highspeed;
182      cd-gpios  = <&gpio2 31 0x4>;
183      st,sig-dir-dat0;
184      st,sig-dir-dat2;
185      st,sig-dir-cmd;
186      st,sig-pin-fbclk;
187      vmmc-supply = <&ab8500_ldo_aux3_reg>;
188      vqmmc-supply = <&vmmci>;
189    };
190
191    mmc@101f6000 {
192      compatible = "arm,pl18x", "arm,primecell";
193      reg = <0x101f6000 0x1000>;
194      clocks = <&sdiclk>, <&pclksdi>;
195      clock-names = "mclk", "apb_pclk";
196      interrupt-parent = <&vica>;
197      interrupts = <22>;
198      max-frequency = <400000>;
199      bus-width = <4>;
200      cap-mmc-highspeed;
201      cap-sd-highspeed;
202      full-pwr-cycle;
203      st,sig-dir-dat0;
204      st,sig-dir-dat2;
205      st,sig-dir-dat31;
206      st,sig-dir-cmd;
207      st,sig-pin-fbclk;
208      vmmc-supply = <&vmmc_regulator>;
209    };
210
211    mmc@52007000 {
212      compatible = "arm,pl18x", "arm,primecell";
213      arm,primecell-periphid = <0x10153180>;
214      reg = <0x52007000 0x1000>;
215      interrupts = <49>;
216      interrupt-names = "cmd_irq";
217      clocks = <&rcc 0>;
218      clock-names = "apb_pclk";
219      resets = <&rcc 1>;
220      cap-sd-highspeed;
221      cap-mmc-highspeed;
222      max-frequency = <120000000>;
223    };
224