xref: /freebsd/sys/contrib/device-tree/Bindings/mmc/arm,pl18x.yaml (revision 8bab661a3316d8bd9b9fbd11a3b4371b91507bd2) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/arm,pl18x.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM PrimeCell MultiMedia Card Interface (MMCI) PL180 and PL181
8
9maintainers:
10  - Linus Walleij <linus.walleij@linaro.org>
11  - Ulf Hansson <ulf.hansson@linaro.org>
12
13description:
14  The ARM PrimeCells MMCI PL180 and PL181 provides an interface for
15  reading and writing to MultiMedia and SD cards alike. Over the years
16  vendors have use the VHDL code from ARM to create derivative MMC/SD/SDIO
17  host controllers with very similar characteristics.
18
19allOf:
20  - $ref: /schemas/arm/primecell.yaml#
21  - $ref: mmc-controller.yaml#
22
23# We need a select here so we don't match all nodes with 'arm,primecell'
24select:
25  properties:
26    compatible:
27      contains:
28        enum:
29          - arm,pl180
30          - arm,pl181
31          - arm,pl18x
32  required:
33    - compatible
34
35properties:
36  compatible:
37    oneOf:
38      - description: The first version of the block, simply called
39          PL180 and found in the ARM Integrator IM/PD1 logic module.
40        items:
41          - const: arm,pl180
42          - const: arm,primecell
43      - description: The improved version of the block, found in the
44          ARM Versatile and later reference designs. Further revisions
45          exist but get detected at runtime by reading some magic numbers
46          in the PrimeCell ID registers.
47        items:
48          - const: arm,pl181
49          - const: arm,primecell
50      - description: Wildcard entry that will let the operating system
51          inspect the PrimeCell ID registers to determine which hardware
52          variant of PL180 or PL181 this is.
53        items:
54          - const: arm,pl18x
55          - const: arm,primecell
56      - description: Entry for STMicroelectronics variant of PL18x.
57          This dedicated compatible is used by bootloaders.
58        items:
59          - const: st,stm32-sdmmc2
60          - const: arm,pl18x
61          - const: arm,primecell
62
63  clocks:
64    description: One or two clocks, the "apb_pclk" and the "MCLK"
65      which is the core block clock. The names are not compulsory.
66    minItems: 1
67    maxItems: 2
68
69  dmas:
70    maxItems: 2
71
72  dma-names:
73    oneOf:
74      - items:
75          - const: tx
76          - const: rx
77      - items:
78          - const: rx
79          - const: tx
80
81  power-domains: true
82
83  resets:
84    maxItems: 1
85
86  reg:
87    description: the MMIO memory window must be exactly 4KB (0x1000) and the
88      layout should provide the PrimeCell ID registers so that the device can
89      be discovered. On ST Micro variants, a second register window may be
90      defined if a delay block is present and used for tuning.
91
92  interrupts:
93    description: The first interrupt is the command interrupt and corresponds
94      to the event at the end of a command. The second interrupt is the
95      PIO (polled I/O) interrupt and occurs when the FIFO needs to be
96      emptied as part of a bulk read from the card. Some variants have these
97      two interrupts wired into the same line (logic OR) and in that case
98      only one interrupt may be provided. The interrupt-names property is
99      not used due to inconsistency of existing DTs regarding its content.
100    deprecated: false
101    minItems: 1
102    maxItems: 2
103
104  st,sig-dir-dat0:
105    $ref: /schemas/types.yaml#/definitions/flag
106    description: ST Micro-specific property, bus signal direction pins used for
107      DAT[0].
108
109  st,sig-dir-dat2:
110    $ref: /schemas/types.yaml#/definitions/flag
111    description: ST Micro-specific property, bus signal direction pins used for
112      DAT[2].
113
114  st,sig-dir-dat31:
115    $ref: /schemas/types.yaml#/definitions/flag
116    description: ST Micro-specific property, bus signal direction pins used for
117      DAT[3] and DAT[1].
118
119  st,sig-dir-dat74:
120    $ref: /schemas/types.yaml#/definitions/flag
121    description: ST Micro-specific property, bus signal direction pins used for
122      DAT[7] and DAT[4].
123
124  st,sig-dir-cmd:
125    $ref: /schemas/types.yaml#/definitions/flag
126    description: ST Micro-specific property, CMD signal direction used for
127      pin CMD.
128
129  st,sig-pin-fbclk:
130    $ref: /schemas/types.yaml#/definitions/flag
131    description: ST Micro-specific property, feedback clock FBCLK signal pin
132      in use.
133
134  st,sig-dir:
135    $ref: /schemas/types.yaml#/definitions/flag
136    description: ST Micro-specific property, signal direction polarity used for
137      pins CMD, DAT[0], DAT[1], DAT[2] and DAT[3].
138
139  st,neg-edge:
140    $ref: /schemas/types.yaml#/definitions/flag
141    description: ST Micro-specific property, data and command phase relation,
142      generated on the sd clock falling edge.
143
144  st,use-ckin:
145    $ref: /schemas/types.yaml#/definitions/flag
146    description: ST Micro-specific property, use CKIN pin from an external
147      driver to sample the receive data (for example with a voltage switch
148      transceiver).
149
150  st,cmd-gpios:
151    maxItems: 1
152    description:
153      The GPIO matching the CMD pin.
154
155  st,ck-gpios:
156    maxItems: 1
157    description:
158      The GPIO matching the CK pin.
159
160  st,ckin-gpios:
161    maxItems: 1
162    description:
163      The GPIO matching the CKIN pin.
164
165dependencies:
166  st,cmd-gpios: [ "st,use-ckin" ]
167  st,ck-gpios: [ "st,use-ckin" ]
168  st,ckin-gpios: [ "st,use-ckin" ]
169
170unevaluatedProperties: false
171
172required:
173  - compatible
174  - reg
175  - interrupts
176
177examples:
178  - |
179    #include <dt-bindings/interrupt-controller/irq.h>
180    #include <dt-bindings/gpio/gpio.h>
181
182    mmc@5000 {
183      compatible = "arm,pl180", "arm,primecell";
184      reg = <0x5000 0x1000>;
185      interrupts-extended = <&vic 22 &sic 1>;
186      clocks = <&xtal24mhz>, <&pclk>;
187      clock-names = "mclk", "apb_pclk";
188    };
189
190  - |
191    #include <dt-bindings/interrupt-controller/irq.h>
192
193    mmc@80126000 {
194      compatible = "arm,pl18x", "arm,primecell";
195      reg = <0x80126000 0x1000>;
196      interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
197      dmas = <&dma 29 0 0x2>, <&dma 29 0 0x0>;
198      dma-names = "rx", "tx";
199      clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
200      clock-names = "sdi", "apb_pclk";
201      max-frequency = <100000000>;
202      bus-width = <4>;
203      cap-sd-highspeed;
204      cap-mmc-highspeed;
205      cd-gpios  = <&gpio2 31 0x4>;
206      st,sig-dir-dat0;
207      st,sig-dir-dat2;
208      st,sig-dir-cmd;
209      st,sig-pin-fbclk;
210      vmmc-supply = <&ab8500_ldo_aux3_reg>;
211      vqmmc-supply = <&vmmci>;
212    };
213
214  - |
215    mmc@101f6000 {
216      compatible = "arm,pl18x", "arm,primecell";
217      reg = <0x101f6000 0x1000>;
218      clocks = <&sdiclk>, <&pclksdi>;
219      clock-names = "mclk", "apb_pclk";
220      interrupts = <22>;
221      max-frequency = <400000>;
222      bus-width = <4>;
223      cap-mmc-highspeed;
224      cap-sd-highspeed;
225      full-pwr-cycle;
226      st,sig-dir-dat0;
227      st,sig-dir-dat2;
228      st,sig-dir-dat31;
229      st,sig-dir-cmd;
230      st,sig-pin-fbclk;
231      vmmc-supply = <&vmmc_regulator>;
232    };
233
234  - |
235    mmc@52007000 {
236      compatible = "arm,pl18x", "arm,primecell";
237      arm,primecell-periphid = <0x10153180>;
238      reg = <0x52007000 0x1000>;
239      interrupts = <49>;
240      clocks = <&rcc 0>;
241      clock-names = "apb_pclk";
242      resets = <&rcc 1>;
243      cap-sd-highspeed;
244      cap-mmc-highspeed;
245      max-frequency = <120000000>;
246    };
247