1* Xilinx SDFEC(16nm) IP * 2 3The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block 4which provides high-throughput LDPC and Turbo Code implementations. 5The LDPC decode & encode functionality is capable of covering a range of 6customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality 7principally covers codes used by LTE. The FEC Engine offers significant 8power and area savings versus implementations done in the FPGA fabric. 9 10 11Required properties: 12- compatible: Must be "xlnx,sd-fec-1.1" 13- clock-names : List of input clock names from the following: 14 - "core_clk", Main processing clock for processing core (required) 15 - "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required) 16 - "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional) 17 - "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional) 18 - "s_axis_ctrl_aclk", Control input AXI4-Stream Slave interface clock (optional) 19 - "m_axis_dout_aclk", DOUT AXI4-Stream Master interface clock (optional) 20 - "m_axis_dout_words_aclk", DOUT_WORDS AXI4-Stream Master interface clock (optional) 21 - "m_axis_status_aclk", Status output AXI4-Stream Master interface clock (optional) 22- clocks : Clock phandles (see clock_bindings.txt for details). 23- reg: Should contain Xilinx SDFEC 16nm Hardened IP block registers 24 location and length. 25- xlnx,sdfec-code : Should contain "ldpc" or "turbo" to describe the codes 26 being used. 27- xlnx,sdfec-din-words : A value 0 indicates that the DIN_WORDS interface is 28 driven with a fixed value and is not present on the device, a value of 1 29 configures the DIN_WORDS to be block based, while a value of 2 configures the 30 DIN_WORDS input to be supplied for each AXI transaction. 31- xlnx,sdfec-din-width : Configures the DIN AXI stream where a value of 1 32 configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width 33 of "4x128b". 34- xlnx,sdfec-dout-words : A value 0 indicates that the DOUT_WORDS interface is 35 driven with a fixed value and is not present on the device, a value of 1 36 configures the DOUT_WORDS to be block based, while a value of 2 configures the 37 DOUT_WORDS input to be supplied for each AXI transaction. 38- xlnx,sdfec-dout-width : Configures the DOUT AXI stream where a value of 1 39 configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width 40 of "4x128b". 41Optional properties: 42- interrupts: should contain SDFEC interrupt number 43 44Example 45--------------------------------------- 46 sd_fec_0: sd-fec@a0040000 { 47 compatible = "xlnx,sd-fec-1.1"; 48 clock-names = "core_clk","s_axi_aclk","s_axis_ctrl_aclk","s_axis_din_aclk","m_axis_status_aclk","m_axis_dout_aclk"; 49 clocks = <&misc_clk_2>,<&misc_clk_0>,<&misc_clk_1>,<&misc_clk_1>,<&misc_clk_1>, <&misc_clk_1>; 50 reg = <0x0 0xa0040000 0x0 0x40000>; 51 interrupt-parent = <&axi_intc>; 52 interrupts = <1 0>; 53 xlnx,sdfec-code = "ldpc"; 54 xlnx,sdfec-din-words = <0>; 55 xlnx,sdfec-din-width = <2>; 56 xlnx,sdfec-dout-words = <0>; 57 xlnx,sdfec-dout-width = <1>; 58 }; 59